📄 key_scan1.tan.rpt
字号:
; N/A ; 92.59 MHz ( period = 10.800 ns ) ; div_clk:inst3|i[7] ; div_clk:inst3|i[25] ; clk_in ; clk_in ; None ; None ; 9.700 ns ;
; N/A ; 93.46 MHz ( period = 10.700 ns ) ; div_clk:inst3|k[12] ; div_clk:inst3|k[31] ; clk_in ; clk_in ; None ; None ; 9.600 ns ;
; N/A ; 93.46 MHz ( period = 10.700 ns ) ; div_clk:inst3|k[3] ; div_clk:inst3|k[22] ; clk_in ; clk_in ; None ; None ; 9.600 ns ;
; N/A ; 93.46 MHz ( period = 10.700 ns ) ; div_clk:inst3|k[9] ; div_clk:inst3|k[28] ; clk_in ; clk_in ; None ; None ; 9.600 ns ;
; N/A ; 93.46 MHz ( period = 10.700 ns ) ; div_clk:inst3|k[11] ; div_clk:inst3|k[30] ; clk_in ; clk_in ; None ; None ; 9.600 ns ;
; N/A ; 93.46 MHz ( period = 10.700 ns ) ; div_clk:inst3|k[0] ; div_clk:inst3|k[23] ; clk_in ; clk_in ; None ; None ; 9.600 ns ;
; N/A ; 93.46 MHz ( period = 10.700 ns ) ; div_clk:inst3|k[7] ; div_clk:inst3|k[24] ; clk_in ; clk_in ; None ; None ; 9.600 ns ;
; N/A ; 93.46 MHz ( period = 10.700 ns ) ; div_clk:inst3|i[1] ; div_clk:inst3|i[20] ; clk_in ; clk_in ; None ; None ; 9.600 ns ;
; N/A ; 93.46 MHz ( period = 10.700 ns ) ; div_clk:inst3|i[2] ; div_clk:inst3|i[21] ; clk_in ; clk_in ; None ; None ; 9.600 ns ;
; N/A ; 93.46 MHz ( period = 10.700 ns ) ; div_clk:inst3|i[5] ; div_clk:inst3|i[23] ; clk_in ; clk_in ; None ; None ; 9.600 ns ;
; N/A ; 93.46 MHz ( period = 10.700 ns ) ; div_clk:inst3|i[9] ; div_clk:inst3|i[28] ; clk_in ; clk_in ; None ; None ; 9.600 ns ;
; N/A ; 93.46 MHz ( period = 10.700 ns ) ; div_clk:inst3|i[12] ; div_clk:inst3|i[30] ; clk_in ; clk_in ; None ; None ; 9.600 ns ;
; N/A ; 93.46 MHz ( period = 10.700 ns ) ; div_clk:inst3|i[8] ; div_clk:inst3|i[26] ; clk_in ; clk_in ; None ; None ; 9.600 ns ;
; N/A ; 94.34 MHz ( period = 10.600 ns ) ; div_clk:inst3|k[1] ; div_clk:inst3|k[19] ; clk_in ; clk_in ; None ; None ; 9.500 ns ;
; N/A ; 94.34 MHz ( period = 10.600 ns ) ; div_clk:inst3|k[2] ; div_clk:inst3|k[21] ; clk_in ; clk_in ; None ; None ; 9.500 ns ;
; N/A ; 94.34 MHz ( period = 10.600 ns ) ; div_clk:inst3|k[4] ; div_clk:inst3|k[22] ; clk_in ; clk_in ; None ; None ; 9.500 ns ;
; N/A ; 94.34 MHz ( period = 10.600 ns ) ; div_clk:inst3|k[8] ; div_clk:inst3|k[27] ; clk_in ; clk_in ; None ; None ; 9.500 ns ;
; N/A ; 94.34 MHz ( period = 10.600 ns ) ; div_clk:inst3|k[10] ; div_clk:inst3|k[29] ; clk_in ; clk_in ; None ; None ; 9.500 ns ;
; N/A ; 94.34 MHz ( period = 10.600 ns ) ; div_clk:inst3|i[4] ; div_clk:inst3|i[21] ; clk_in ; clk_in ; None ; None ; 9.500 ns ;
; N/A ; 94.34 MHz ( period = 10.600 ns ) ; div_clk:inst3|i[10] ; div_clk:inst3|i[29] ; clk_in ; clk_in ; None ; None ; 9.500 ns ;
; N/A ; 94.34 MHz ( period = 10.600 ns ) ; div_clk:inst3|i[11] ; div_clk:inst3|i[30] ; clk_in ; clk_in ; None ; None ; 9.500 ns ;
; N/A ; 94.34 MHz ( period = 10.600 ns ) ; div_clk:inst3|i[7] ; div_clk:inst3|i[24] ; clk_in ; clk_in ; None ; None ; 9.500 ns ;
; N/A ; 94.34 MHz ( period = 10.600 ns ) ; div_clk:inst3|i[0] ; div_clk:inst3|clk_200hz ; clk_in ; clk_in ; None ; None ; 9.500 ns ;
; N/A ; 95.24 MHz ( period = 10.500 ns ) ; div_clk:inst3|i[0] ; div_clk:inst3|i[21] ; clk_in ; clk_in ; None ; None ; 9.400 ns ;
; N/A ; 95.24 MHz ( period = 10.500 ns ) ; div_clk:inst3|i[5] ; div_clk:inst3|i[22] ; clk_in ; clk_in ; None ; None ; 9.400 ns ;
; N/A ; 95.24 MHz ( period = 10.500 ns ) ; div_clk:inst3|i[6] ; div_clk:inst3|i[23] ; clk_in ; clk_in ; None ; None ; 9.400 ns ;
; N/A ; 95.24 MHz ( period = 10.500 ns ) ; div_clk:inst3|i[1] ; div_clk:inst3|i[19] ; clk_in ; clk_in ; None ; None ; 9.400 ns ;
; N/A ; 95.24 MHz ( period = 10.500 ns ) ; div_clk:inst3|i[10] ; div_clk:inst3|i[28] ; clk_in ; clk_in ; None ; None ; 9.400 ns ;
; N/A ; 95.24 MHz ( period = 10.500 ns ) ; div_clk:inst3|i[12] ; div_clk:inst3|i[29] ; clk_in ; clk_in ; None ; None ; 9.400 ns ;
; N/A ; 95.24 MHz ( period = 10.500 ns ) ; div_clk:inst3|i[13] ; div_clk:inst3|i[30] ; clk_in ; clk_in ; None ; None ; 9.400 ns ;
; N/A ; 95.24 MHz ( period = 10.500 ns ) ; div_clk:inst3|i[15] ; div_clk:inst3|i[31] ; clk_in ; clk_in ; None ; None ; 9.400 ns ;
; N/A ; 95.24 MHz ( period = 10.500 ns ) ; div_clk:inst3|i[8] ; div_clk:inst3|i[25] ; clk_in ; clk_in ; None ; None ; 9.400 ns ;
; N/A ; 95.24 MHz ( period = 10.500 ns ) ; div_clk:inst3|i[27] ; div_clk:inst3|clk_200hz ; clk_in ; clk_in ; None ; None ; 9.400 ns ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ; ; ; ; ; ; ; ;
+-----------------------------------------+-----------------------------------------------------+---------------------+-------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
+--------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Hold: 'clk_in' ;
+------------------------------------------+--------------------+---------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Minimum Slack ; From ; To ; From Clock ; To Clock ; Required Hold Relationship ; Required Shortest P2P Time ; Actual Shortest P2P Time ;
+------------------------------------------+--------------------+---------------------------+------------+----------+----------------------------+----------------------------+--------------------------+
; Not operational: Clock Skew > Data Delay ; qudou:6|d:18|q ; key_scan:inst|retn_out[0] ; clk_in ; clk_in ; None ; None ; 1.300 ns ;
; Not operational: Clock Skew > Data Delay ; qudou:6|d:17|q ; key_scan:inst|retn_out[0] ; clk_in ; clk_in ; None ; None ; 2.100 ns ;
; Not operational: Clock Skew > Data Delay ; qudou:10|d:18|q ; key_scan:inst|retn_out[0] ; clk_in ; clk_in ; None ; None ; 3.000 ns ;
; Not operational: Clock Skew > Data Delay ; key_scan:inst|q[0] ; mux1_6:49|out0[2] ; clk_in ; clk_in ; None ; None ; 3.000 ns ;
; Not operational: Clock Skew > Data Delay ; key_scan:inst|q[1] ; mux1_6:49|out0[3] ; clk_in ; clk_in ; None ; None ; 3.000 ns ;
; Not operational: Clock Skew > Data Delay ; qudou:10|d:18|q ; key_scan:inst|retn_out[1] ; clk_in ; clk_in ; None ; None ; 3.200 ns ;
; Not operational: Clock Skew > Data Delay ; qudou:6|d:18|q ; key_scan:inst|retn_out[1] ; clk_in ; clk_in ; None ; None ; 3.300 ns ;
; Not operational: Clock Skew > Data Delay ; qudou:10|d:17|q ; key_scan:inst|retn_out[0] ; clk_in ; clk_in ; None ; None ; 3.600 ns ;
; Not operational: Clock Skew > Data Delay ; qudou:13|d:17|q ; key_scan:inst|retn_out[1] ; clk_in ; clk_in ; None ; None ; 3.600 ns ;
; Not operational: Clock Skew > Data Delay ; mux1_6:49|out1[0] ; mux1_6:49|out2[0] ; clk_in ; clk_in ; None ; None ; 1.100 ns ;
; Not operational: Clock Skew > Data Delay ; mux1_6:49|out0[0] ; mux1_6:49|out1[0] ; clk_in ; clk_in ; None ; None ; 1.100 ns ;
; Not operational: Clock Skew > Data Delay ; mux1_6:49|out4[0] ; mux1_6:49|out5[0] ; clk_in ; clk_in ; None ; None ; 1.100 ns ;
; Not operational: Clock Skew > Data Delay ; mux1_6:49|out1[1] ; mux1_6:49|out2[1] ; clk_in ; clk_in ; None ; None ; 1.100 ns ;
; Not operational: Clock Skew > Data Delay ; mux1_6:49|out0[1] ; mux1_6:49|out1[1] ; clk_in ; clk_in ; None ; None ; 1.100 ns ;
; Not operational: Clock Skew > Data Delay ; mux1_6:49|out2[1] ; mux1_6:49|out3[1] ; clk_in ; clk_in ; None ; None ; 1.100 ns ;
; Not operational: Clock Skew > Data Delay ; mux1_6:49|out3[1] ; mux1_6:49|out4[1] ; clk_in ; clk_in ; None ; None ; 1.100 ns ;
; Not operational: Clock Skew > Data Delay ; mux1_6:49|out2[2] ; mux1_6:49|out3[2] ; clk_in ; clk_in ; None ; None ; 1.100 ns ;
; Not operational: Clock Skew > Data Delay ; mux1_6:49|out4[2] ; mux1_6:49|out5[2] ; clk_in ; clk_in ; None ; None ; 1.100 ns ;
; Not operational: Clock Skew > Data Delay ; mux1_6:49|out3[2] ; mux1_6:49|out4[2] ; clk_in ; clk_in ; None ; None ; 1.100 ns ;
; Not operational: Clock Skew > Data Delay ; mux1_6:49|out2[3] ; mux1_6:49|out3[3] ; clk_in ; clk_in ; None ; None ; 1.100 ns ;
; Not operational: Clock Skew > Data ⌨️ 快捷键说明
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