key_scan1.tan.rpt

来自「用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功」· RPT 代码 · 共 323 行 · 第 1/5 页

; Use Fast Timing Models                                ; Off                ;      ;    ;             ;
; Report IO Paths Separately                            ; Off                ;      ;    ;             ;
; Default hold multicycle                               ; Same as Multicycle ;      ;    ;             ;
; Cut paths between unrelated clock domains             ; On                 ;      ;    ;             ;
; Cut off read during write signal paths                ; On                 ;      ;    ;             ;
; Cut off feedback from I/O pins                        ; On                 ;      ;    ;             ;
; Report Combined Fast/Slow Timing                      ; Off                ;      ;    ;             ;
; Ignore Clock Settings                                 ; Off                ;      ;    ;             ;
; Analyze latches as synchronous elements               ; Off                ;      ;    ;             ;
; Enable Recovery/Removal analysis                      ; Off                ;      ;    ;             ;
; Enable Clock Latency                                  ; Off                ;      ;    ;             ;
+-------------------------------------------------------+--------------------+------+----+-------------+


+------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Settings Summary                                                                                                                                                             ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; Clock Node Name ; Clock Setting Name ; Type     ; Fmax Requirement ; Early Latency ; Late Latency ; Based on ; Multiply Base Fmax by ; Divide Base Fmax by ; Offset ; Phase offset ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+
; clk_in          ;                    ; User Pin ; NONE             ; 0.000 ns      ; 0.000 ns     ; NONE     ; N/A                   ; N/A                 ; N/A    ;              ;
+-----------------+--------------------+----------+------------------+---------------+--------------+----------+-----------------------+---------------------+--------+--------------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Clock Setup: 'clk_in'                                                                                                                                                                                                                                     ;
+-----------------------------------------+-----------------------------------------------------+---------------------+-------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; Slack                                   ; Actual fmax (period)                                ; From                ; To                      ; From Clock ; To Clock ; Required Setup Relationship ; Required Longest P2P Time ; Actual Longest P2P Time ;
+-----------------------------------------+-----------------------------------------------------+---------------------+-------------------------+------------+----------+-----------------------------+---------------------------+-------------------------+
; N/A                                     ; 74.63 MHz ( period = 13.400 ns )                    ; div_clk:inst3|k[1]  ; div_clk:inst3|k[31]     ; clk_in     ; clk_in   ; None                        ; None                      ; 12.300 ns               ;
; N/A                                     ; 75.19 MHz ( period = 13.300 ns )                    ; div_clk:inst3|i[1]  ; div_clk:inst3|i[31]     ; clk_in     ; clk_in   ; None                        ; None                      ; 12.200 ns               ;
; N/A                                     ; 75.76 MHz ( period = 13.200 ns )                    ; div_clk:inst3|k[1]  ; div_clk:inst3|k[30]     ; clk_in     ; clk_in   ; None                        ; None                      ; 12.100 ns               ;
; N/A                                     ; 76.34 MHz ( period = 13.100 ns )                    ; div_clk:inst3|k[2]  ; div_clk:inst3|k[31]     ; clk_in     ; clk_in   ; None                        ; None                      ; 12.000 ns               ;
; N/A                                     ; 76.34 MHz ( period = 13.100 ns )                    ; div_clk:inst3|i[2]  ; div_clk:inst3|i[31]     ; clk_in     ; clk_in   ; None                        ; None                      ; 12.000 ns               ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; div_clk:inst3|k[3]  ; div_clk:inst3|k[31]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.900 ns               ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; div_clk:inst3|i[1]  ; div_clk:inst3|i[30]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.900 ns               ;
; N/A                                     ; 76.92 MHz ( period = 13.000 ns )                    ; div_clk:inst3|i[4]  ; div_clk:inst3|i[31]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.900 ns               ;
; N/A                                     ; 77.52 MHz ( period = 12.900 ns )                    ; div_clk:inst3|k[4]  ; div_clk:inst3|k[31]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.800 ns               ;
; N/A                                     ; 77.52 MHz ( period = 12.900 ns )                    ; div_clk:inst3|k[1]  ; div_clk:inst3|k[29]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.800 ns               ;
; N/A                                     ; 77.52 MHz ( period = 12.900 ns )                    ; div_clk:inst3|k[2]  ; div_clk:inst3|k[30]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.800 ns               ;
; N/A                                     ; 77.52 MHz ( period = 12.900 ns )                    ; div_clk:inst3|i[3]  ; div_clk:inst3|i[31]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.800 ns               ;
; N/A                                     ; 77.52 MHz ( period = 12.900 ns )                    ; div_clk:inst3|i[0]  ; div_clk:inst3|i[31]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.800 ns               ;
; N/A                                     ; 78.13 MHz ( period = 12.800 ns )                    ; div_clk:inst3|k[0]  ; div_clk:inst3|k[31]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.700 ns               ;
; N/A                                     ; 78.13 MHz ( period = 12.800 ns )                    ; div_clk:inst3|k[1]  ; div_clk:inst3|k[28]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.700 ns               ;
; N/A                                     ; 78.13 MHz ( period = 12.800 ns )                    ; div_clk:inst3|k[3]  ; div_clk:inst3|k[30]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.700 ns               ;
; N/A                                     ; 78.13 MHz ( period = 12.800 ns )                    ; div_clk:inst3|i[1]  ; div_clk:inst3|i[29]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.700 ns               ;
; N/A                                     ; 78.13 MHz ( period = 12.800 ns )                    ; div_clk:inst3|i[2]  ; div_clk:inst3|i[30]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.700 ns               ;
; N/A                                     ; 78.74 MHz ( period = 12.700 ns )                    ; div_clk:inst3|k[4]  ; div_clk:inst3|k[30]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.600 ns               ;
; N/A                                     ; 78.74 MHz ( period = 12.700 ns )                    ; div_clk:inst3|i[1]  ; div_clk:inst3|i[28]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.600 ns               ;
; N/A                                     ; 78.74 MHz ( period = 12.700 ns )                    ; div_clk:inst3|i[4]  ; div_clk:inst3|i[30]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.600 ns               ;
; N/A                                     ; 79.37 MHz ( period = 12.600 ns )                    ; div_clk:inst3|k[2]  ; div_clk:inst3|k[29]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.500 ns               ;
; N/A                                     ; 79.37 MHz ( period = 12.600 ns )                    ; div_clk:inst3|k[0]  ; div_clk:inst3|k[30]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.500 ns               ;
; N/A                                     ; 79.37 MHz ( period = 12.600 ns )                    ; div_clk:inst3|i[2]  ; div_clk:inst3|i[29]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.500 ns               ;
; N/A                                     ; 79.37 MHz ( period = 12.600 ns )                    ; div_clk:inst3|i[3]  ; div_clk:inst3|i[30]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.500 ns               ;
; N/A                                     ; 79.37 MHz ( period = 12.600 ns )                    ; div_clk:inst3|i[0]  ; div_clk:inst3|i[30]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.500 ns               ;
; N/A                                     ; 79.37 MHz ( period = 12.600 ns )                    ; div_clk:inst3|i[5]  ; div_clk:inst3|i[31]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.500 ns               ;
; N/A                                     ; 80.00 MHz ( period = 12.500 ns )                    ; div_clk:inst3|k[5]  ; div_clk:inst3|k[31]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.400 ns               ;
; N/A                                     ; 80.00 MHz ( period = 12.500 ns )                    ; div_clk:inst3|k[1]  ; div_clk:inst3|k[27]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.400 ns               ;
; N/A                                     ; 80.00 MHz ( period = 12.500 ns )                    ; div_clk:inst3|k[2]  ; div_clk:inst3|k[28]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.400 ns               ;
; N/A                                     ; 80.00 MHz ( period = 12.500 ns )                    ; div_clk:inst3|k[3]  ; div_clk:inst3|k[29]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.400 ns               ;
; N/A                                     ; 80.00 MHz ( period = 12.500 ns )                    ; div_clk:inst3|i[2]  ; div_clk:inst3|i[28]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.400 ns               ;
; N/A                                     ; 80.00 MHz ( period = 12.500 ns )                    ; div_clk:inst3|i[4]  ; div_clk:inst3|i[29]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.400 ns               ;
; N/A                                     ; 80.65 MHz ( period = 12.400 ns )                    ; div_clk:inst3|k[6]  ; div_clk:inst3|k[31]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.300 ns               ;
; N/A                                     ; 80.65 MHz ( period = 12.400 ns )                    ; div_clk:inst3|k[3]  ; div_clk:inst3|k[28]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.300 ns               ;
; N/A                                     ; 80.65 MHz ( period = 12.400 ns )                    ; div_clk:inst3|k[4]  ; div_clk:inst3|k[29]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.300 ns               ;
; N/A                                     ; 80.65 MHz ( period = 12.400 ns )                    ; div_clk:inst3|i[4]  ; div_clk:inst3|i[28]     ; clk_in     ; clk_in   ; None                        ; None                      ; 11.300 ns               ;