key_scan1.tan.rpt
来自「用verilog实现的四乘四键盘程序,在Quartus II上编译通过并成功」· RPT 代码 · 共 323 行 · 第 1/5 页
RPT
323 行
; N/A ; 80.65 MHz ( period = 12.400 ns ) ; div_clk:inst3|i[3] ; div_clk:inst3|i[29] ; clk_in ; clk_in ; None ; None ; 11.300 ns ;
; N/A ; 80.65 MHz ( period = 12.400 ns ) ; div_clk:inst3|i[0] ; div_clk:inst3|i[29] ; clk_in ; clk_in ; None ; None ; 11.300 ns ;
; N/A ; 80.65 MHz ( period = 12.400 ns ) ; div_clk:inst3|i[6] ; div_clk:inst3|i[31] ; clk_in ; clk_in ; None ; None ; 11.300 ns ;
; N/A ; 80.65 MHz ( period = 12.400 ns ) ; div_clk:inst3|i[1] ; div_clk:inst3|i[27] ; clk_in ; clk_in ; None ; None ; 11.300 ns ;
; N/A ; 81.30 MHz ( period = 12.300 ns ) ; div_clk:inst3|k[4] ; div_clk:inst3|k[28] ; clk_in ; clk_in ; None ; None ; 11.200 ns ;
; N/A ; 81.30 MHz ( period = 12.300 ns ) ; div_clk:inst3|k[0] ; div_clk:inst3|k[29] ; clk_in ; clk_in ; None ; None ; 11.200 ns ;
; N/A ; 81.30 MHz ( period = 12.300 ns ) ; div_clk:inst3|k[5] ; div_clk:inst3|k[30] ; clk_in ; clk_in ; None ; None ; 11.200 ns ;
; N/A ; 81.30 MHz ( period = 12.300 ns ) ; div_clk:inst3|k[1] ; div_clk:inst3|k[26] ; clk_in ; clk_in ; None ; None ; 11.200 ns ;
; N/A ; 81.30 MHz ( period = 12.300 ns ) ; div_clk:inst3|i[3] ; div_clk:inst3|i[28] ; clk_in ; clk_in ; None ; None ; 11.200 ns ;
; N/A ; 81.30 MHz ( period = 12.300 ns ) ; div_clk:inst3|i[0] ; div_clk:inst3|i[28] ; clk_in ; clk_in ; None ; None ; 11.200 ns ;
; N/A ; 81.30 MHz ( period = 12.300 ns ) ; div_clk:inst3|i[5] ; div_clk:inst3|i[30] ; clk_in ; clk_in ; None ; None ; 11.200 ns ;
; N/A ; 81.97 MHz ( period = 12.200 ns ) ; div_clk:inst3|k[7] ; div_clk:inst3|k[31] ; clk_in ; clk_in ; None ; None ; 11.100 ns ;
; N/A ; 81.97 MHz ( period = 12.200 ns ) ; div_clk:inst3|k[2] ; div_clk:inst3|k[27] ; clk_in ; clk_in ; None ; None ; 11.100 ns ;
; N/A ; 81.97 MHz ( period = 12.200 ns ) ; div_clk:inst3|k[0] ; div_clk:inst3|k[28] ; clk_in ; clk_in ; None ; None ; 11.100 ns ;
; N/A ; 81.97 MHz ( period = 12.200 ns ) ; div_clk:inst3|k[6] ; div_clk:inst3|k[30] ; clk_in ; clk_in ; None ; None ; 11.100 ns ;
; N/A ; 81.97 MHz ( period = 12.200 ns ) ; div_clk:inst3|i[1] ; div_clk:inst3|i[26] ; clk_in ; clk_in ; None ; None ; 11.100 ns ;
; N/A ; 81.97 MHz ( period = 12.200 ns ) ; div_clk:inst3|i[2] ; div_clk:inst3|i[27] ; clk_in ; clk_in ; None ; None ; 11.100 ns ;
; N/A ; 82.64 MHz ( period = 12.100 ns ) ; div_clk:inst3|k[3] ; div_clk:inst3|k[27] ; clk_in ; clk_in ; None ; None ; 11.000 ns ;
; N/A ; 82.64 MHz ( period = 12.100 ns ) ; div_clk:inst3|k[1] ; div_clk:inst3|k[25] ; clk_in ; clk_in ; None ; None ; 11.000 ns ;
; N/A ; 82.64 MHz ( period = 12.100 ns ) ; div_clk:inst3|i[5] ; div_clk:inst3|i[29] ; clk_in ; clk_in ; None ; None ; 11.000 ns ;
; N/A ; 82.64 MHz ( period = 12.100 ns ) ; div_clk:inst3|i[6] ; div_clk:inst3|i[30] ; clk_in ; clk_in ; None ; None ; 11.000 ns ;
; N/A ; 82.64 MHz ( period = 12.100 ns ) ; div_clk:inst3|i[7] ; div_clk:inst3|i[31] ; clk_in ; clk_in ; None ; None ; 11.000 ns ;
; N/A ; 82.64 MHz ( period = 12.100 ns ) ; div_clk:inst3|i[4] ; div_clk:inst3|i[27] ; clk_in ; clk_in ; None ; None ; 11.000 ns ;
; N/A ; 83.33 MHz ( period = 12.000 ns ) ; div_clk:inst3|k[4] ; div_clk:inst3|k[27] ; clk_in ; clk_in ; None ; None ; 10.900 ns ;
; N/A ; 83.33 MHz ( period = 12.000 ns ) ; div_clk:inst3|k[5] ; div_clk:inst3|k[29] ; clk_in ; clk_in ; None ; None ; 10.900 ns ;
; N/A ; 83.33 MHz ( period = 12.000 ns ) ; div_clk:inst3|k[7] ; div_clk:inst3|k[30] ; clk_in ; clk_in ; None ; None ; 10.900 ns ;
; N/A ; 83.33 MHz ( period = 12.000 ns ) ; div_clk:inst3|k[2] ; div_clk:inst3|k[26] ; clk_in ; clk_in ; None ; None ; 10.900 ns ;
; N/A ; 83.33 MHz ( period = 12.000 ns ) ; div_clk:inst3|i[5] ; div_clk:inst3|i[28] ; clk_in ; clk_in ; None ; None ; 10.900 ns ;
; N/A ; 83.33 MHz ( period = 12.000 ns ) ; div_clk:inst3|i[1] ; div_clk:inst3|i[25] ; clk_in ; clk_in ; None ; None ; 10.900 ns ;
; N/A ; 83.33 MHz ( period = 12.000 ns ) ; div_clk:inst3|i[2] ; div_clk:inst3|i[26] ; clk_in ; clk_in ; None ; None ; 10.900 ns ;
; N/A ; 83.33 MHz ( period = 12.000 ns ) ; div_clk:inst3|i[3] ; div_clk:inst3|i[27] ; clk_in ; clk_in ; None ; None ; 10.900 ns ;
; N/A ; 83.33 MHz ( period = 12.000 ns ) ; div_clk:inst3|i[0] ; div_clk:inst3|i[27] ; clk_in ; clk_in ; None ; None ; 10.900 ns ;
; N/A ; 84.03 MHz ( period = 11.900 ns ) ; div_clk:inst3|k[0] ; div_clk:inst3|k[27] ; clk_in ; clk_in ; None ; None ; 10.800 ns ;
; N/A ; 84.03 MHz ( period = 11.900 ns ) ; div_clk:inst3|k[5] ; div_clk:inst3|k[28] ; clk_in ; clk_in ; None ; None ; 10.800 ns ;
; N/A ; 84.03 MHz ( period = 11.900 ns ) ; div_clk:inst3|k[6] ; div_clk:inst3|k[29] ; clk_in ; clk_in ; None ; None ; 10.800 ns ;
; N/A ; 84.03 MHz ( period = 11.900 ns ) ; div_clk:inst3|k[1] ; div_clk:inst3|k[24] ; clk_in ; clk_in ; None ; None ; 10.800 ns ;
; N/A ; 84.03 MHz ( period = 11.900 ns ) ; div_clk:inst3|k[3] ; div_clk:inst3|k[26] ; clk_in ; clk_in ; None ; None ; 10.800 ns ;
; N/A ; 84.03 MHz ( period = 11.900 ns ) ; div_clk:inst3|i[6] ; div_clk:inst3|i[29] ; clk_in ; clk_in ; None ; None ; 10.800 ns ;
; N/A ; 84.03 MHz ( period = 11.900 ns ) ; div_clk:inst3|i[4] ; div_clk:inst3|i[26] ; clk_in ; clk_in ; None ; None ; 10.800 ns ;
; N/A ; 84.75 MHz ( period = 11.800 ns ) ; div_clk:inst3|k[6] ; div_clk:inst3|k[28] ; clk_in ; clk_in ; None ; None ; 10.700 ns ;
; N/A ; 84.75 MHz ( period = 11.800 ns ) ; div_clk:inst3|k[2] ; div_clk:inst3|k[25] ; clk_in ; clk_in ; None ; None ; 10.700 ns ;
; N/A ; 84.75 MHz ( period = 11.800 ns ) ; div_clk:inst3|k[4] ; div_clk:inst3|k[26] ; clk_in ; clk_in ; None ; None ; 10.700 ns ;
; N/A ; 84.75 MHz ( period = 11.800 ns ) ; div_clk:inst3|i[6] ; div_clk:inst3|i[28] ; clk_in ; clk_in ; None ; None ; 10.700 ns ;
; N/A ; 84.75 MHz ( period = 11.800 ns ) ; div_clk:inst3|i[7] ; div_clk:inst3|i[30] ; clk_in ; clk_in ; None ; None ; 10.700 ns ;
; N/A ; 84.75 MHz ( period = 11.800 ns ) ; div_clk:inst3|i[8] ; div_clk:inst3|i[31] ; clk_in ; clk_in ; None ; None ; 10.700 ns ;
; N/A ; 84.75 MHz ( period = 11.800 ns ) ; div_clk:inst3|i[1] ; div_clk:inst3|i[24] ; clk_in ; clk_in ; None ; None ; 10.700 ns ;
; N/A ; 84.75 MHz ( period = 11.800 ns ) ; div_clk:inst3|i[2] ; div_clk:inst3|i[25] ; clk_in ; clk_in ; None ; None ; 10.700 ns ;
; N/A ; 84.75 MHz ( period = 11.800 ns ) ; div_clk:inst3|i[3] ; div_clk:inst3|i[26] ; clk_in ; clk_in ; None ; None ; 10.700 ns ;
; N/A ; 84.75 MHz ( period = 11.800 ns ) ; div_clk:inst3|i[0] ; div_clk:inst3|i[26] ; clk_in ; clk_in ; None ; None ; 10.700 ns ;
; N/A ; 85.47 MHz ( period = 11.700 ns ) ; div_clk:inst3|k[7] ; div_clk:inst3|k[29] ; clk_in ; clk_in ; None ; None ; 10.600 ns ;
; N/A ; 85.47 MHz ( period = 11.700 ns ) ; div_clk:inst3|k[3] ; div_clk:inst3|k[25] ; clk_in ; clk_in ; None ; None ; 10.600 ns ;
; N/A ; 85.47 MHz ( period = 11.700 ns ) ; div_clk:inst3|k[0] ; div_clk:inst3|k[26] ; clk_in ; clk_in ; None ; None ; 10.600 ns ;
; N/A ; 85.47 MHz ( period = 11.700 ns ) ; div_clk:inst3|i[4] ; div_clk:inst3|i[25] ; clk_in ; clk_in ; None ; None ; 10.600 ns ;
; N/A ; 85.47 MHz ( period = 11.700 ns ) ; div_clk:inst3|i[5] ; div_clk:inst3|i[27] ; clk_in ; clk_in ; None ; None ; 10.600 ns ;
; N/A ; 86.21 MHz ( period = 11.600 ns ) ; div_clk:inst3|k[5] ; div_clk:inst3|k[27] ; clk_in ; clk_in ; None ; None ; 10.500 ns ;
; N/A ; 86.21 MHz ( period = 11.600 ns ) ; div_clk:inst3|k[7] ; div_clk:inst3|k[28] ; clk_in ; clk_in ; None ; None ; 10.500 ns ;
; N/A ; 86.21 MHz ( period = 11.600 ns ) ; div_clk:inst3|k[2] ; div_clk:inst3|k[24] ; clk_in ; clk_in ; None ; None ; 10.500 ns ;
; N/A ; 86.21 MHz ( period = 11.600 ns ) ; div_clk:inst3|k[4] ; div_clk:inst3|k[25] ; clk_in ; clk_in ; None ; None ; 10.500 ns ;
; N/A ; 86.21 MHz ( period = 11.600 ns ) ; div_clk:inst3|i[7] ; div_clk:inst3|i[29] ; clk_in ; clk_in ; None ; None ; 10.500 ns ;
; N/A ; 86.21 MHz ( period = 11.600 ns ) ; div_clk:inst3|i[2] ; div_clk:inst3|i[24] ; clk_in ; clk_in ; None ; None ; 10.500 ns ;
; N/A ; 86.21 MHz ( period = 11.600 ns ) ; div_clk:inst3|i[3] ; div_clk:inst3|i[25] ; clk_in ; clk_in ; None ; None ; 10.500 ns ;
; N/A ; 86.21 MHz ( period = 11.600 ns ) ; div_clk:inst3|i[0] ; div_clk:inst3|i[25] ; clk_in ; clk_in ; None ; None ; 10.500 ns ;
; N/A ; 86.96 MHz ( period = 11.500 ns ) ; div_clk:inst3|k[8] ; div_clk:inst3|k[31] ; clk_in ; clk_in ; None ; None ; 10.400 ns ;
; N/A ; 86.96 MHz ( period = 11.500 ns ) ; div_clk:inst3|k[6] ; div_clk:inst3|k[27] ; clk_in ; clk_in ; None ; None ; 10.400 ns ;
; N/A ; 86.96 MHz ( period = 11.500 ns ) ; div_clk:inst3|k[3] ; div_clk:inst3|k[24] ; clk_in ; clk_in ; None ; None ; 10.400 ns ;
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