add_full_n.vhd

来自「该程序实现的是n位全加器」· VHDL 代码 · 共 48 行

library ieee;
use ieee.std_logic_1164.all;

entity add_full_n is
generic(n:integer:=8);
port(x,y:in std_logic_vector(n-1 downto 0);
	 c_in:in std_logic;
	 s:out std_logic_vector(n-1 downto 0);
	 c_out:out std_logic);
end add_full_n;


architecture arch_add_full_n of add_full_n is
component add_full
port(x,y:in std_logic;
     c_in : in std_logic;
	 s: out std_logic;
	 c_out: out std_logic);
end component;
signal carry:std_logic_vector(n-2 downto 0);
begin
gen: for i in 0 to n-1 generate
first : if i=0 generate
first_cell:add_full
port map(x(i),y(i),c_in,s(i),carry(i));
end generate first;

last : if i=n-1 generate
last_cell:add_full
port map(x(i),y(i),carry(n-1),s(i),c_out);
end generate last;

middle : if i>0 and i<n-1 generate
middle_cell:add_full
port map(x(i),y(i),carry(i-1),s(i),carry(i));
end generate middle;




end generate gen;





end arch_add_full_n;