add_full.vhd

来自「该程序实现的是n位全加器」· VHDL 代码 · 共 31 行

library ieee;
use ieee.std_logic_1164.all;

entity add_full is
generic(d_time:time:=5 ns);
port(x,y:in std_logic;
     c_in : in std_logic;
	 s: out std_logic;
	 c_out: out std_logic);
end add_full;



architecture arch_add_full of add_full is
component not_and
port(a,b:in std_logic;
	 c: out std_logic); 
end component;
signal a1,a2,a3,a5,a6,a7,a8:std_logic;
begin
U1:not_and port map(x,y,a1);
U2:not_and port map(x,a1,a2);
U3:not_and port map(y,a1,a3);
U4:not_and port map(a2,a3,a5);
U5:not_and port map(c_in,a5,a6);
U6:not_and port map(c_in,a6,a7);
U7:not_and port map(a6,a5,a8);
U8:not_and port map(a7,a8,s);
U9:not_and port map(a6,a1,c_out);
end arch_add_full;