not_and.vhd

来自「该程序实现的是n位全加器」· VHDL 代码 · 共 13 行

library ieee;
use ieee.std_logic_1164.all;
entity not_and is
generic(d_time:time:=5 ns);
port(a,b:in std_logic;
	 c: out std_logic);
end not_and;

architecture arch_not_and of not_and is
begin
c<=a nand b after d_time;
end arch_not_and;