not_and.tlg

该程序实现的是n位全加器

@N:"D:\VHDL_EXERCISE\add_full_n\add_full_n.vhd":4:7:4:16|Synthesizing work.add_full_n.arch_add_full_n 
@W: CD280 :"D:\VHDL_EXERCISE\add_full_n\add_full_n.vhd":14:10:14:17|Unbound component add_full mapped to black box
@W: CD453 :"D:\VHDL_EXERCISE\add_full_n\add_full_n.vhd":30:19:30:23|Index 7 may be out of range
@N:"D:\VHDL_EXERCISE\add_full_n\add_full_n.vhd":14:10:14:17|Synthesizing work.add_full.syn_black_box 
Post processing for work.add_full.syn_black_box
Post processing for work.add_full_n.arch_add_full_n
@W: CL167 :"D:\VHDL_EXERCISE\add_full_n\add_full_n.vhd":29:0:29:8|Input c_in of instance last_cell is floating