not_and.srd

该程序实现的是n位全加器

f "noname"; #file 0
f "d:\program files\synplicity\fpga_81\lib\vhd\std.vhd"; #file 1
f "d:\vhdl_exercise\add_full_n\add_full_n.vhd"; #file 2
f "d:\program files\synplicity\fpga_81\lib\vhd\std1164.vhd"; #file 3
f "d:\vhdl_exercise\add_full_n\not_and.vhd"; #file 4
f "d:\vhdl_exercise\add_full_n\add_full.vhd"; #file 5
VNAME 'work.add_full.syn_black_box'; # view id 0
VNAME 'work.add_full_n.arch_add_full_n'; # view id 1
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