not_and.srr

该程序实现的是n位全加器

#Program: Synplify Pro 8.1
#OS: Windows_NT

$ Start of Compile
#Tue Nov 01 17:53:25 2005

Synplicity VHDL Compiler, version 3.1.0, Build 049R, built May  3 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved

@N:"D:\VHDL_EXERCISE\add_full_n\add_full_n.vhd":4:7:4:16|Top entity is set to add_full_n.
VHDL syntax check successful!
File D:\VHDL_EXERCISE\add_full_n\not_and.vhd changed - recompiling
@N:"D:\VHDL_EXERCISE\add_full_n\add_full_n.vhd":4:7:4:16|Synthesizing work.add_full_n.arch_add_full_n 
@W: CD280 :"D:\VHDL_EXERCISE\add_full_n\add_full_n.vhd":14:10:14:17|Unbound component add_full mapped to black box
@W: CD453 :"D:\VHDL_EXERCISE\add_full_n\add_full_n.vhd":30:19:30:23|Index 7 may be out of range
@N:"D:\VHDL_EXERCISE\add_full_n\add_full_n.vhd":14:10:14:17|Synthesizing work.add_full.syn_black_box 
Post processing for work.add_full.syn_black_box
Post processing for work.add_full_n.arch_add_full_n
@W: CL167 :"D:\VHDL_EXERCISE\add_full_n\add_full_n.vhd":29:0:29:8|Input c_in of instance last_cell is floating
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Tue Nov 01 17:53:26 2005

###########################################################[
Version 8.1
Synplicity Proasic Technology Mapper, Version 8.1.0, Build 539R, Built May  6 2005
Copyright (C) 1994-2005, Synplicity Inc.  All Rights Reserved
@W: BN215 |Library scaling: cannot find default operating conditions - failed to scale design


RTL optimization done.

Added 0 Buffers
Added 0 Cells via replication
Writing Analyst data base D:\VHDL_EXERCISE\add_full_n\rev_1\not_and.srm
Writing EDIF Netlist and constraint files
@W: MT253 :"d:\vhdl_exercise\add_full_n\add_full_n.vhd":34:0:34:10|Blackbox add_full is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) 


##### START OF TIMING REPORT #####[
# Timing Report written on Tue Nov 01 17:53:27 2005
#


Top view:               add_full_n
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        5
Constraint File(s):    
@N: MT195 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..

@N: MT197 |Clock constraints cover only FF-to-FF paths associated with the clock..



Performance Summary 
*******************


Worst slack in design: 993.370

                   Requested     Estimated     Requested     Estimated                 Clock      Clock           
Starting Clock     Frequency     Frequency     Period        Period        Slack       Type       Group           
------------------------------------------------------------------------------------------------------------------
System             1.0 MHz       150.8 MHz     1000.000      6.630         993.370     system     default_clkgroup
==================================================================================================================





Interface Information 
*********************

		No IO constraint found 



====================================
Detailed Report for Clock: System
====================================



Starting Points with Worst Slack
********************************

                             Starting                                          Arrival            
Instance                     Reference     Type         Pin       Net          Time        Slack  
                             Clock                                                                
--------------------------------------------------------------------------------------------------
gen.0.first.first_cell       System        add_full     c_out     carry[0]     3.000       993.370
gen.1.middle.middle_cell     System        add_full     c_out     carry[1]     3.000       993.370
gen.2.middle.middle_cell     System        add_full     c_out     carry[2]     3.000       993.370
gen.3.middle.middle_cell     System        add_full     c_out     carry[3]     3.000       993.370
gen.4.middle.middle_cell     System        add_full     c_out     carry[4]     3.000       993.370
gen.5.middle.middle_cell     System        add_full     c_out     carry[5]     3.000       993.370
==================================================================================================


Ending Points with Worst Slack
******************************

                             Starting                                         Required            
Instance                     Reference     Type         Pin      Net          Time         Slack  
                             Clock                                                                
--------------------------------------------------------------------------------------------------
gen.1.middle.middle_cell     System        add_full     c_in     carry[0]     997.000      993.370
gen.2.middle.middle_cell     System        add_full     c_in     carry[1]     997.000      993.370
gen.3.middle.middle_cell     System        add_full     c_in     carry[2]     997.000      993.370
gen.4.middle.middle_cell     System        add_full     c_in     carry[3]     997.000      993.370
gen.5.middle.middle_cell     System        add_full     c_in     carry[4]     997.000      993.370
gen.6.middle.middle_cell     System        add_full     c_in     carry[5]     997.000      993.370
==================================================================================================



Worst Path Information
***********************


Path information for path number 1: 
    Requested Period:                        1000.000
    - Setup time:                            3.000
    = Required time:                         997.000

    - Propagation time:                      3.630
    = Slack (critical) :                     993.370

    Number of logic level(s):                0
    Starting point:                          gen.0.first.first_cell / c_out
    Ending point:                            gen.1.middle.middle_cell / c_in
    The start point is clocked by            System [rising]
    The end   point is clocked by            System [rising]

Instance / Net                            Pin       Pin               Arrival     No. of    
Name                         Type         Name      Dir     Delay     Time        Fan Out(s)
--------------------------------------------------------------------------------------------
gen.0.first.first_cell       add_full     c_out     Out     0.000     3.000       -         
carry[0]                     Net          -         -       0.630     -           1         
gen.1.middle.middle_cell     add_full     c_in      In      -         3.630       -         
============================================================================================
Total path delay (propagation time + setup) of 6.630 is 3.000(45.2%) logic and 0.630(9.5%) route.



##### END OF TIMING REPORT #####]

--------------------------------------------------------------------------------
Report for cell add_full_n.arch_add_full_n
  Cell usage:
              cell count     area count*area
              IB33    17      0.0        0.0
            OB33PH     9      0.0        0.0
          add_full     8      0.0        0.0
               PWR     1      0.0        0.0
               GND     1      0.0        0.0
                   -----          ----------
             TOTAL    36                 0.0
Mapper successful!
Process took 0h:0m:0s realtime, 0h:0m:0s cputime
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