tb_add_full_n.vhd

该程序实现的是n位全加器

library ieee;
use ieee.std_logic_1164.all;

entity test is
end test;

architecture arch_test of test is
component add_full_n
generic(n:integer:=2);
port(x,y:in std_logic_vector(n-1 downto 0);
	 c_in:in std_logic;
	 s:out std_logic_vector(n-1 downto 0);
	 c_out:out std_logic);     
end component;
signal x,y,s:std_logic_vector(n-1 downto 0);
signal c_in,c_out:std_logic;
begin
U1:add_full_n port map(x,y,c_in,s,c_out);
c_in<='1','0'after 240 ns;
x<="01","11"after 80 ns,"10"after 240 ns, "11" after 320 ns;
y<="00","10"after 160 ns,"01"after 240 ns,"01" after 400 ns;
end arch_test;

configuration cfg_test of test is
for arch_test
end for;
end cfg_test;