registers.v

Use the verilog language write a MIPS CPU code, and have additional instruction, for example: select

/**************************************************/
// MODULE:        Register Bank for MIPS ISA
//
// AUTHOR:        Hsieh Tsung Ming
// DESCRIPTION:   Implement register bank for
//                for single-cycle processor
/*************************************************/

module Registers ( Read_register1, Read_register2, Write_register,
		   Write_data, 
                   RegWrite,
		   Clk, 
                   Read_data1, Read_data2 );
   // INPUTS
   input [4:0] Read_register1, Read_register2, Write_register;
   input [31:0] Write_data;
   input 	RegWrite;
   input 	Clk;
   // OUTPUT
   output [31:0] Read_data1, Read_data2;

   // SIGNAL DECLARATIONS
   reg [31:0] 	 Read_data1, Read_data2;
   

   // Register Bank
   //*********************************************
   reg [31:0] 	 REGISTER_BANK [0:31];
   //*********************************************

   // MAIN CODE
   
   // ZERO REGISTER
   initial
      begin
	 REGISTER_BANK[0] = 32'h00000000;
      end // initial begin
   

   always @( Clk or Read_register1 or Read_register2 )
      begin
	 Read_data1 = REGISTER_BANK[Read_register1];
	 Read_data2 = REGISTER_BANK[Read_register2];
      end // always @ ( Read_register1 or Read_register2 )
   
   always @( posedge Clk )
      begin
	 if ( (RegWrite == 1'b1) && ( Write_register != 5'b00000) )
	    REGISTER_BANK[Write_register] = Write_data;
      end // always @ ( posedge CLK )
   
endmodule // REGISTERS