pc.v

Use the verilog language write a MIPS CPU code, and have additional instruction, for example: select

//=============================================================================
//PC Module
//	input CLK;
//	input [31:0] dataIn;
//	output[31:0] dataOut;
//=============================================================================

module Pc( CLK, dataIn, dataOut );
	input CLK;	
	input [31:0] dataIn;
	output[31:0] dataOut;
	reg [31:0] dataOut;

	initial	dataOut = 32'h00000004;

	always @( posedge CLK )	
		begin
			dataOut = dataIn;
		end

endmodule