qdq.rpt

采用Verilog HDL设计,在掌宇智能开发板上得到实现 根据抢答器的原理

-- Equation name is '_LC5_C3', type is buried 
_LC5_C3  = LCELL( _EQ013);
  _EQ013 =  _LC3_C2 & !s1 &  s2 & !s3;

-- Node name is '|decoder:54|:72' 
-- Equation name is '_LC6_C3', type is buried 
_LC6_C3  = LCELL( _EQ014);
  _EQ014 =  _LC3_C2 & !s1 & !s2 &  s3;

-- Node name is '|decoder:54|:96' 
-- Equation name is '_LC2_C2', type is buried 
_LC2_C2  = LCELL( _EQ015);
  _EQ015 =  _LC6_C1 &  _LC7_C2 &  s4 & !s5;

-- Node name is '|decoder:54|:120' 
-- Equation name is '_LC4_C2', type is buried 
_LC4_C2  = LCELL( _EQ016);
  _EQ016 =  _LC6_C1 &  _LC7_C2 & !s4 &  s5;

-- Node name is '|decoder:54|:168' 
-- Equation name is '_LC4_C1', type is buried 
_LC4_C1  = LCELL( _EQ017);
  _EQ017 =  _LC5_C2 & !s6 &  s7 & !s8;

-- Node name is '|decoder:54|~192~1' 
-- Equation name is '_LC7_C2', type is buried 
-- synthesized logic cell 
_LC7_C2  = LCELL( _EQ018);
  _EQ018 = !s1 & !s2 & !s3;

-- Node name is '|decoder:54|~192~2' 
-- Equation name is '_LC5_C2', type is buried 
-- synthesized logic cell 
_LC5_C2  = LCELL( _EQ019);
  _EQ019 =  _LC7_C2 & !s4 & !s5;

-- Node name is '|decoder:54|:192' 
-- Equation name is '_LC3_C1', type is buried 
_LC3_C1  = LCELL( _EQ020);
  _EQ020 =  _LC5_C2 & !s6 & !s7 &  s8;

-- Node name is '|decoder:54|:248' 
-- Equation name is '_LC1_C3', type is buried 
_LC1_C3  = LCELL( _EQ021);
  _EQ021 =  _LC6_C3
         #  _LC4_C2
         #  _LC1_C1
         #  _LC4_C1;

-- Node name is '|decoder:54|~249~1' 
-- Equation name is '_LC8_C3', type is buried 
-- synthesized logic cell 
_LC8_C3  = LCELL( _EQ022);
  _EQ022 =  _LC3_C2 &  s1 & !s2 & !s3
         #  _LC3_C2 & !s1 & !s2 &  s3;

-- Node name is '|decoder:54|~249~2' 
-- Equation name is '_LC2_C3', type is buried 
-- synthesized logic cell 
_LC2_C3  = LCELL( _EQ023);
  _EQ023 =  _LC8_C3
         #  _LC4_C1;

-- Node name is '|decoder:54|:249' 
-- Equation name is '_LC3_C3', type is buried 
_LC3_C3  = LCELL( _EQ024);
  _EQ024 =  _LC2_C3
         #  _LC3_C1
         #  _LC2_C2
         #  _LC5_C3;

-- Node name is '|decoder:54|:250' 
-- Equation name is '_LC5_C1', type is buried 
_LC5_C1  = LCELL( _EQ025);
  _EQ025 =  _LC2_C3
         #  _LC2_C1;

-- Node name is '|decoder:54|:251' 
-- Equation name is '_LC7_C3', type is buried 
_LC7_C3  = LCELL( _EQ026);
  _EQ026 =  _LC1_C1
         #  _LC6_C3
         #  _LC4_C2;

-- Node name is '|decoder:54|:252' 
-- Equation name is '_LC1_C1', type is buried 
_LC1_C1  = LCELL( _EQ027);
  _EQ027 =  _LC5_C3
         #  _LC8_C1;

-- Node name is '|decoder:54|~253~1' 
-- Equation name is '_LC8_C1', type is buried 
-- synthesized logic cell 
_LC8_C1  = LCELL( _EQ028);
  _EQ028 =  _LC3_C1
         #  _LC5_C2 &  _LC7_C1 &  s6;

-- Node name is '|decoder:54|:253' 
-- Equation name is '_LC2_C1', type is buried 
_LC2_C1  = LCELL( _EQ029);
  _EQ029 =  _LC2_C2
         #  _LC4_C2
         #  _LC8_C1;

-- Node name is '|decoder:54|:254' 
-- Equation name is '_LC4_C3', type is buried 
_LC4_C3  = LCELL( _EQ030);
  _EQ030 =  _LC2_C2
         #  _LC7_C3;

-- Node name is '~29~1' 
-- Equation name is '~29~1', location is LC5_C11, type is buried.
-- synthesized logic cell 
_LC5_C11 = LCELL( _EQ031);
  _EQ031 = !_LC7_C11
         # !_LC8_C11
         # !_LC6_C11;

-- Node name is '~29~2' 
-- Equation name is '~29~2', location is LC5_C9, type is buried.
-- synthesized logic cell 
_LC5_C9  = LCELL( _EQ032);
  _EQ032 = !_LC8_C9
         # !_LC8_C2
         # !_LC7_C9;

-- Node name is ':39' 
-- Equation name is '_LC7_C9', type is buried 
!_LC7_C9 = _LC7_C9~NOT;
_LC7_C9~NOT = LCELL( _EQ033);
  _EQ033 = !resetn &  s1;

-- Node name is ':41' 
-- Equation name is '_LC8_C9', type is buried 
!_LC8_C9 = _LC8_C9~NOT;
_LC8_C9~NOT = LCELL( _EQ034);
  _EQ034 = !resetn &  s2;

-- Node name is ':43' 
-- Equation name is '_LC6_C11', type is buried 
!_LC6_C11 = _LC6_C11~NOT;
_LC6_C11~NOT = LCELL( _EQ035);
  _EQ035 = !_LC6_C11 & !resetn
         # !ctrl & !resetn & !s3n;

-- Node name is ':45' 
-- Equation name is '_LC6_C2', type is buried 
!_LC6_C2 = _LC6_C2~NOT;
_LC6_C2~NOT = LCELL( _EQ036);
  _EQ036 = !resetn &  s4;

-- Node name is ':47' 
-- Equation name is '_LC8_C2', type is buried 
!_LC8_C2 = _LC8_C2~NOT;
_LC8_C2~NOT = LCELL( _EQ037);
  _EQ037 = !resetn &  s5;

-- Node name is ':49' 
-- Equation name is '_LC6_C9', type is buried 
!_LC6_C9 = _LC6_C9~NOT;
_LC6_C9~NOT = LCELL( _EQ038);
  _EQ038 = !resetn &  s6;

-- Node name is ':50' 
-- Equation name is '_LC7_C11', type is buried 
!_LC7_C11 = _LC7_C11~NOT;
_LC7_C11~NOT = LCELL( _EQ039);
  _EQ039 = !resetn &  s7;

-- Node name is ':53' 
-- Equation name is '_LC8_C11', type is buried 
!_LC8_C11 = _LC8_C11~NOT;
_LC8_C11~NOT = LCELL( _EQ040);
  _EQ040 = !resetn &  s8;



Project Information                                 f:\verilog hdl\qdq\qdq.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:00
   Fitter                                 00:00:01
   Timing SNF Extractor                   00:00:01
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:02


Memory Allocated
-----------------

Peak memory allocated during compilation  = 15,187K