📄 qdq.rpt
字号:
49 - - - 16 OUTPUT 0 0 0 0 o7
47 - - - 14 OUTPUT 0 0 0 0 o8
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information: f:\verilog hdl\qdq\qdq.rpt
qdq
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 6 - C 01 AND2 s 0 3 0 3 |decoder:54|~24~1
- 3 - C 02 AND2 s 0 3 0 3 |decoder:54|~24~2
- 7 - C 01 AND2 s 0 2 0 1 |decoder:54|~24~3
- 5 - C 03 AND2 0 4 0 2 |decoder:54|:48
- 6 - C 03 AND2 0 4 0 2 |decoder:54|:72
- 2 - C 02 AND2 0 4 0 3 |decoder:54|:96
- 4 - C 02 AND2 0 4 0 3 |decoder:54|:120
- 4 - C 01 AND2 0 4 0 2 |decoder:54|:168
- 7 - C 02 AND2 s 0 3 0 3 |decoder:54|~192~1
- 5 - C 02 AND2 s 0 3 0 3 |decoder:54|~192~2
- 3 - C 01 AND2 0 4 0 2 |decoder:54|:192
- 1 - C 03 OR2 0 4 1 0 |decoder:54|:248
- 8 - C 03 OR2 s 0 4 0 1 |decoder:54|~249~1
- 2 - C 03 OR2 s 0 2 0 2 |decoder:54|~249~2
- 3 - C 03 OR2 0 4 1 0 |decoder:54|:249
- 5 - C 01 OR2 0 2 1 0 |decoder:54|:250
- 7 - C 03 OR2 0 3 1 1 |decoder:54|:251
- 1 - C 01 OR2 0 2 1 2 |decoder:54|:252
- 8 - C 01 OR2 s 0 4 0 2 |decoder:54|~253~1
- 2 - C 01 OR2 0 3 1 1 |decoder:54|:253
- 4 - C 03 OR2 0 2 1 0 |decoder:54|:254
- 3 - C 11 LCELL 1 2 0 4 s3 (:1)
- 4 - C 09 LCELL 0 4 0 9 ctrl (:2)
- 5 - C 11 OR2 s 0 3 0 1 ~29~1
- 5 - C 09 OR2 s 0 3 0 1 ~29~2
- 2 - C 09 OR2 1 2 0 5 s1 (:38)
- 7 - C 09 AND2 ! 1 1 0 2 :39
- 3 - C 09 OR2 1 2 0 5 s2 (:40)
- 8 - C 09 AND2 ! 1 1 0 2 :41
- 6 - C 11 OR2 ! 2 1 0 2 :43
- 4 - C 11 OR2 1 2 0 5 s4 (:44)
- 6 - C 02 AND2 ! 1 1 0 2 :45
- 1 - C 02 OR2 1 2 0 5 s5 (:46)
- 8 - C 02 AND2 ! 1 1 0 2 :47
- 1 - C 09 OR2 1 2 0 5 s6 (:48)
- 6 - C 09 AND2 ! 1 1 0 2 :49
- 7 - C 11 AND2 ! 1 1 0 2 :50
- 2 - C 11 OR2 1 2 0 5 s7 (:51)
- 1 - C 11 OR2 1 2 0 5 s8 (:52)
- 8 - C 11 AND2 ! 1 1 0 2 :53
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information: f:\verilog hdl\qdq\qdq.rpt
qdq
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 4/ 48( 8%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 0/ 96( 0%) 3/ 48( 6%) 0/ 48( 0%) 0/16( 0%) 5/16( 31%) 0/16( 0%)
C: 6/ 96( 6%) 23/ 48( 47%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 4/24( 16%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
02: 2/24( 8%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
03: 6/24( 25%) 2/4( 50%) 0/4( 0%) 0/4( 0%)
04: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
05: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 1/24( 4%) 1/4( 25%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information: f:\verilog hdl\qdq\qdq.rpt
qdq
** EQUATIONS **
resetn : INPUT;
s1n : INPUT;
s2n : INPUT;
s3n : INPUT;
s4n : INPUT;
s5n : INPUT;
s6n : INPUT;
s7n : INPUT;
s8n : INPUT;
-- Node name is 'a'
-- Equation name is 'a', type is output
a = _LC1_C3;
-- Node name is 'b'
-- Equation name is 'b', type is output
b = _LC3_C3;
-- Node name is 'c'
-- Equation name is 'c', type is output
c = _LC5_C1;
-- Node name is ':2' = 'ctrl'
-- Equation name is 'ctrl', location is LC4_C9, type is buried.
ctrl = LCELL( _EQ001);
_EQ001 = !_LC6_C9
# _LC5_C11
# !_LC6_C2
# _LC5_C9;
-- Node name is 'd'
-- Equation name is 'd', type is output
d = _LC7_C3;
-- Node name is 'e'
-- Equation name is 'e', type is output
e = _LC1_C1;
-- Node name is 'f'
-- Equation name is 'f', type is output
f = _LC2_C1;
-- Node name is 'g'
-- Equation name is 'g', type is output
g = _LC4_C3;
-- Node name is 'o1'
-- Equation name is 'o1', type is output
o1 = VCC;
-- Node name is 'o2'
-- Equation name is 'o2', type is output
o2 = VCC;
-- Node name is 'o3'
-- Equation name is 'o3', type is output
o3 = VCC;
-- Node name is 'o4'
-- Equation name is 'o4', type is output
o4 = VCC;
-- Node name is 'o5'
-- Equation name is 'o5', type is output
o5 = VCC;
-- Node name is 'o6'
-- Equation name is 'o6', type is output
o6 = VCC;
-- Node name is 'o7'
-- Equation name is 'o7', type is output
o7 = VCC;
-- Node name is 'o8'
-- Equation name is 'o8', type is output
o8 = VCC;
-- Node name is ':38' = 's1'
-- Equation name is 's1', location is LC2_C9, type is buried.
s1 = LCELL( _EQ002);
_EQ002 = !_LC7_C9
# !ctrl & !s1n;
-- Node name is ':40' = 's2'
-- Equation name is 's2', location is LC3_C9, type is buried.
s2 = LCELL( _EQ003);
_EQ003 = !_LC8_C9
# !ctrl & !s2n;
-- Node name is ':1' = 's3'
-- Equation name is 's3', location is LC3_C11, type is buried.
s3 = LCELL( _EQ004);
_EQ004 = !ctrl & !s3n
# !_LC6_C11;
-- Node name is ':44' = 's4'
-- Equation name is 's4', location is LC4_C11, type is buried.
s4 = LCELL( _EQ005);
_EQ005 = !_LC6_C2
# !ctrl & !s4n;
-- Node name is ':46' = 's5'
-- Equation name is 's5', location is LC1_C2, type is buried.
s5 = LCELL( _EQ006);
_EQ006 = !_LC8_C2
# !ctrl & !s5n;
-- Node name is ':48' = 's6'
-- Equation name is 's6', location is LC1_C9, type is buried.
s6 = LCELL( _EQ007);
_EQ007 = !_LC6_C9
# !ctrl & !s6n;
-- Node name is ':51' = 's7'
-- Equation name is 's7', location is LC2_C11, type is buried.
s7 = LCELL( _EQ008);
_EQ008 = !_LC7_C11
# !ctrl & !s7n;
-- Node name is ':52' = 's8'
-- Equation name is 's8', location is LC1_C11, type is buried.
s8 = LCELL( _EQ009);
_EQ009 = !_LC8_C11
# !ctrl & !s8n;
-- Node name is '|decoder:54|~24~1'
-- Equation name is '_LC6_C1', type is buried
-- synthesized logic cell
_LC6_C1 = LCELL( _EQ010);
_EQ010 = !s6 & !s7 & !s8;
-- Node name is '|decoder:54|~24~2'
-- Equation name is '_LC3_C2', type is buried
-- synthesized logic cell
_LC3_C2 = LCELL( _EQ011);
_EQ011 = _LC6_C1 & !s4 & !s5;
-- Node name is '|decoder:54|~24~3'
-- Equation name is '_LC7_C1', type is buried
-- synthesized logic cell
_LC7_C1 = LCELL( _EQ012);
_EQ012 = !s7 & !s8;
-- Node name is '|decoder:54|:48'
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