clkscan2_top.rpt
来自「此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路」· RPT 代码 · 共 1,198 行 · 第 1/4 页
RPT
1,198 行
# _LC2_A2 & !_LC4_A24 & _LC8_A24;
-- Node name is '|clkscan2:10|:101'
-- Equation name is '_LC1_A24', type is buried
!_LC1_A24 = _LC1_A24~NOT;
_LC1_A24~NOT = LCELL( _EQ059);
_EQ059 = _LC3_A24 & _LC8_A24
# _LC4_A24 & _LC8_A24
# _LC2_A24;
-- Node name is '|clkscan2:10|:156'
-- Equation name is '_LC8_A2', type is buried
_LC8_A2 = DFFE( _EQ060, !_LC6_B10, GLOBAL(!reset), VCC, _LC3_A2);
_EQ060 = _LC2_A24 & _LC3_A24 & _LC4_A24;
-- Node name is '|clkscan2:10|:157'
-- Equation name is '_LC1_A2', type is buried
_LC1_A2 = DFFE( _EQ061, !_LC6_B10, GLOBAL(!reset), VCC, _LC3_A2);
_EQ061 = !_LC2_A2 & !_LC4_A24 & _LC5_A24;
-- Node name is '|clkscan2:10|:158'
-- Equation name is '_LC2_A22', type is buried
_LC2_A22 = DFFE( _EQ062, !_LC6_B10, GLOBAL(!reset), VCC, _LC3_A2);
_EQ062 = _LC2_A2 & _LC4_A24 & !_LC5_A24;
-- Node name is '|clkscan2:10|:159'
-- Equation name is '_LC6_A24', type is buried
_LC6_A24 = DFFE( _EQ063, !_LC6_B10, GLOBAL(!reset), VCC, _LC3_A2);
_EQ063 = _LC2_A2 & !_LC4_A24 & !_LC5_A24;
-- Node name is '|clkscan2:10|:160'
-- Equation name is '_LC7_A24', type is buried
_LC7_A24 = DFFE( _EQ064, !_LC6_B10, GLOBAL(!reset), VCC, _LC3_A2);
_EQ064 = _LC2_A24 & !_LC3_A24 & _LC4_A24;
-- Node name is '|clkscan2:10|:161'
-- Equation name is '_LC8_A23', type is buried
!_LC8_A23 = _LC8_A23~NOT;
_LC8_A23~NOT = DFFE(!_LC1_A24, !_LC6_B10, GLOBAL(!reset), VCC, _LC3_A2);
-- Node name is '|p7segment:3|:144'
-- Equation name is '_LC5_A9', type is buried
!_LC5_A9 = _LC5_A9~NOT;
_LC5_A9~NOT = LCELL( _EQ065);
_EQ065 = !_LC4_A22
# !_LC5_A22
# _LC1_A22
# !_LC3_A22;
-- Node name is '|p7segment:3|~218~1'
-- Equation name is '_LC4_A9', type is buried
-- synthesized logic cell
_LC4_A9 = LCELL( _EQ066);
_EQ066 = !_LC1_A22
# _LC3_A22
# !_LC4_A22 & !_LC5_A22
# _LC4_A22 & _LC5_A22;
-- Node name is '|p7segment:3|~218~2'
-- Equation name is '_LC7_A9', type is buried
-- synthesized logic cell
_LC7_A9 = LCELL( _EQ067);
_EQ067 = !_LC1_A22
# !_LC3_A22
# _LC4_A22 & !_LC5_A22;
-- Node name is '|p7segment:3|:218'
-- Equation name is '_LC1_A9', type is buried
!_LC1_A9 = _LC1_A9~NOT;
_LC1_A9~NOT = LCELL( _EQ068);
_EQ068 = _LC4_A9 & !_LC5_A9 & !_LC6_A9 & _LC7_A9;
-- Node name is '|p7segment:3|~227~1'
-- Equation name is '_LC6_A10', type is buried
-- synthesized logic cell
_LC6_A10 = LCELL( _EQ069);
_EQ069 = !_LC1_A22 & !_LC4_A22 & !_LC5_A22
# !_LC1_A22 & _LC3_A22 & !_LC4_A22
# !_LC1_A22 & _LC3_A22 & !_LC5_A22
# _LC1_A22 & !_LC3_A22 & !_LC4_A22 & _LC5_A22
# _LC1_A22 & !_LC3_A22 & _LC4_A22 & !_LC5_A22;
-- Node name is '|p7segment:3|~227~2'
-- Equation name is '_LC7_A10', type is buried
-- synthesized logic cell
_LC7_A10 = LCELL( _EQ070);
_EQ070 = _LC1_A22 & _LC3_A22 & !_LC4_A22
# _LC1_A22 & _LC3_A22 & _LC5_A22
# _LC1_A22 & _LC4_A22 & _LC5_A22
# !_LC3_A22 & _LC4_A22 & _LC5_A22
# !_LC1_A22 & !_LC3_A22 & _LC5_A22;
-- Node name is '|p7segment:3|:227'
-- Equation name is '_LC1_A10', type is buried
_LC1_A10 = LCELL( _EQ071);
_EQ071 = !_LC1_A9 & _LC1_A10
# _LC7_A10
# _LC6_A10;
-- Node name is '|p7segment:3|~230~1'
-- Equation name is '_LC6_A9', type is buried
-- synthesized logic cell
!_LC6_A9 = _LC6_A9~NOT;
_LC6_A9~NOT = LCELL( _EQ072);
_EQ072 = _LC1_A22 & _LC3_A22 & !_LC4_A22
# _LC1_A22 & !_LC3_A22 & _LC4_A22 & !_LC5_A22
# _LC1_A22 & !_LC4_A22 & _LC5_A22
# _LC1_A22 & _LC3_A22 & _LC5_A22
# _LC3_A22 & _LC4_A22 & _LC5_A22;
-- Node name is '|p7segment:3|:230'
-- Equation name is '_LC3_A9', type is buried
_LC3_A9 = LCELL( _EQ073);
_EQ073 = !_LC1_A9 & _LC3_A9
# _LC6_A9;
-- Node name is '|p7segment:3|~233~1'
-- Equation name is '_LC2_A10', type is buried
-- synthesized logic cell
_LC2_A10 = LCELL( _EQ074);
_EQ074 = _LC6_A10
# _LC3_A10;
-- Node name is '|p7segment:3|~233~2'
-- Equation name is '_LC4_A6', type is buried
-- synthesized logic cell
_LC4_A6 = LCELL( _EQ075);
_EQ075 = !_LC3_A22 & _LC4_A22 & _LC5_A22
# !_LC1_A22 & !_LC3_A22 & _LC4_A22
# _LC1_A22 & _LC3_A22 & _LC4_A22 & !_LC5_A22;
-- Node name is '|p7segment:3|:233'
-- Equation name is '_LC8_A6', type is buried
_LC8_A6 = LCELL( _EQ076);
_EQ076 = !_LC1_A9 & _LC8_A6
# _LC4_A6
# _LC2_A10;
-- Node name is '|p7segment:3|~236~1'
-- Equation name is '_LC3_A6', type is buried
-- synthesized logic cell
_LC3_A6 = LCELL( _EQ077);
_EQ077 = _LC1_A22 & _LC3_A22 & !_LC4_A22
# _LC1_A22 & !_LC4_A22 & _LC5_A22
# !_LC1_A22 & !_LC4_A22 & !_LC5_A22
# !_LC1_A22 & _LC3_A22 & !_LC5_A22
# !_LC1_A22 & !_LC3_A22 & _LC5_A22
# _LC1_A22 & _LC4_A22 & !_LC5_A22
# !_LC1_A22 & _LC4_A22 & _LC5_A22;
-- Node name is '|p7segment:3|:236'
-- Equation name is '_LC6_A6', type is buried
_LC6_A6 = LCELL( _EQ078);
_EQ078 = !_LC1_A9 & _LC6_A6
# _LC3_A6;
-- Node name is '|p7segment:3|~239~1'
-- Equation name is '_LC2_A6', type is buried
-- synthesized logic cell
_LC2_A6 = LCELL( _EQ079);
_EQ079 = !_LC1_A22 & !_LC4_A22
# !_LC4_A22 & _LC5_A22
# _LC3_A22 & _LC5_A22
# _LC1_A22 & _LC3_A22
# _LC3_A22 & !_LC4_A22;
-- Node name is '|p7segment:3|:239'
-- Equation name is '_LC1_A6', type is buried
_LC1_A6 = LCELL( _EQ080);
_EQ080 = _LC1_A6 & !_LC1_A9
# _LC2_A6;
-- Node name is '|p7segment:3|~242~1'
-- Equation name is '_LC3_A10', type is buried
-- synthesized logic cell
_LC3_A10 = LCELL( _EQ081);
_EQ081 = _LC1_A22 & !_LC3_A22 & !_LC4_A22 & !_LC5_A22
# !_LC1_A22 & _LC3_A22 & _LC4_A22 & _LC5_A22;
-- Node name is '|p7segment:3|:242'
-- Equation name is '_LC2_A9', type is buried
_LC2_A9 = LCELL( _EQ082);
_EQ082 = !_LC1_A9 & _LC2_A9
# _LC2_A10
# !_LC7_A9;
-- Node name is '|p7segment:3|~245~1'
-- Equation name is '_LC5_A10', type is buried
-- synthesized logic cell
_LC5_A10 = LCELL( _EQ083);
_EQ083 = !_LC1_A22 & _LC3_A22 & !_LC5_A22
# _LC1_A22 & _LC4_A22 & !_LC5_A22
# _LC1_A22 & _LC3_A22 & _LC5_A22
# !_LC1_A22 & !_LC3_A22 & _LC5_A22
# !_LC1_A22 & _LC3_A22 & !_LC4_A22
# !_LC4_A22 & _LC5_A22
# _LC3_A22 & _LC4_A22 & !_LC5_A22;
-- Node name is '|p7segment:3|:245'
-- Equation name is '_LC4_A10', type is buried
_LC4_A10 = LCELL( _EQ084);
_EQ084 = !_LC1_A9 & _LC4_A10
# _LC3_A10
# _LC5_A10;
Project Informatione:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\clkscan\clkscan2\clkscan2_top.rpt
** COMPILATION SETTINGS & TIMES **
Processing Menu Commands
------------------------
Design Doctor = off
Logic Synthesis:
Synthesis Type Used = Multi-Level
Default Synthesis Style = NORMAL
Logic option settings in 'NORMAL' style for 'FLEX10K' family
CARRY_CHAIN = ignore
CARRY_CHAIN_LENGTH = 32
CASCADE_CHAIN = ignore
CASCADE_CHAIN_LENGTH = 2
DECOMPOSE_GATES = on
DUPLICATE_LOGIC_EXTRACTION = on
MINIMIZATION = full
MULTI_LEVEL_FACTORING = on
NOT_GATE_PUSH_BACK = on
REDUCE_LOGIC = on
REFACTORIZATION = on
REGISTER_OPTIMIZATION = on
RESYNTHESIZE_NETWORK = on
SLOW_SLEW_RATE = off
SUBFACTOR_EXTRACTION = on
IGNORE_SOFT_BUFFERS = on
USE_LPM_FOR_AHDL_OPERATORS = off
Other logic synthesis settings:
Automatic Global Clock = on
Automatic Global Clear = on
Automatic Global Preset = on
Automatic Global Output Enable = on
Automatic Fast I/O = off
Automatic Register Packing = off
Automatic Open-Drain Pins = on
Automatic Implement in EAB = off
Optimize = 5
Default Timing Specifications: None
Cut All Bidir Feedback Timing Paths = on
Cut All Clear & Preset Timing Paths = on
Ignore Timing Assignments = off
Functional SNF Extractor = off
Linked SNF Extractor = off
Timing SNF Extractor = on
Optimize Timing SNF = off
Generate AHDL TDO File = off
Fitter Settings = NORMAL
Use Quartus Fitter = on
Smart Recompile = off
Total Recompile = off
Interfaces Menu Commands
------------------------
EDIF Netlist Writer = off
Verilog Netlist Writer = off
VHDL Netlist Writer = off
Compilation Times
-----------------
Compiler Netlist Extractor 00:00:00
Database Builder 00:00:01
Logic Synthesizer 00:00:00
Partitioner 00:00:00
Fitter 00:00:02
Timing SNF Extractor 00:00:01
Assembler 00:00:00
-------------------------- --------
Total Time 00:00:04
Memory Allocated
-----------------
Peak memory allocated during compilation = 26,701K
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