clkscan2_top.rpt
来自「此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路」· RPT 代码 · 共 1,198 行 · 第 1/4 页
RPT
1,198 行
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\clkscan\clkscan2\clkscan2_top.rpt
clkscan2_top
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 1 - B 04 OR2 ! 0 2 0 3 |clkdiv:2|lpm_add_sub:209|addcore:adder|:135
- 3 - B 04 OR2 ! 0 3 0 2 |clkdiv:2|lpm_add_sub:209|addcore:adder|:143
- 2 - B 04 OR2 ! 0 2 0 4 |clkdiv:2|lpm_add_sub:209|addcore:adder|:147
- 8 - B 06 AND2 0 4 0 4 |clkdiv:2|lpm_add_sub:209|addcore:adder|:159
- 3 - B 07 AND2 0 2 0 1 |clkdiv:2|lpm_add_sub:209|addcore:adder|:163
- 1 - B 07 AND2 0 4 0 4 |clkdiv:2|lpm_add_sub:209|addcore:adder|:171
- 3 - B 08 AND2 0 3 0 1 |clkdiv:2|lpm_add_sub:209|addcore:adder|:179
- 6 - B 08 AND2 0 4 0 4 |clkdiv:2|lpm_add_sub:209|addcore:adder|:183
- 6 - B 01 AND2 0 3 0 1 |clkdiv:2|lpm_add_sub:209|addcore:adder|:191
- 4 - B 01 AND2 0 4 0 3 |clkdiv:2|lpm_add_sub:209|addcore:adder|:195
- 5 - B 07 AND2 0 3 0 4 |clkdiv:2|lpm_add_sub:209|addcore:adder|:203
- 4 - B 10 AND2 0 3 0 1 |clkdiv:2|lpm_add_sub:209|addcore:adder|:211
- 2 - B 10 AND2 0 4 0 2 |clkdiv:2|lpm_add_sub:209|addcore:adder|:215
- 7 - B 10 OR2 0 4 0 24 |clkdiv:2|:12
- 1 - B 01 OR2 0 4 0 2 |clkdiv:2|:27
- 3 - B 01 OR2 s 0 4 0 1 |clkdiv:2|~34~1
- 2 - B 08 OR2 0 4 0 1 |clkdiv:2|:54
- 8 - B 07 OR2 0 4 0 1 |clkdiv:2|:69
- 2 - B 06 AND2 0 3 0 1 |clkdiv:2|:84
- 1 - B 06 OR2 0 3 0 2 |clkdiv:2|:97
- 8 - B 10 DFFE + 0 3 0 2 |clkdiv:2|clk_count23 (|clkdiv:2|:181)
- 3 - B 10 DFFE + 0 2 0 3 |clkdiv:2|clk_count22 (|clkdiv:2|:182)
- 5 - B 10 DFFE + 0 2 0 3 |clkdiv:2|clk_count21 (|clkdiv:2|:183)
- 1 - B 10 DFFE + 0 3 0 3 |clkdiv:2|clk_count20 (|clkdiv:2|:184)
- 6 - B 06 DFFE + 0 2 0 4 |clkdiv:2|clk_count19 (|clkdiv:2|:185)
- 7 - B 07 DFFE + 0 3 0 2 |clkdiv:2|clk_count18 (|clkdiv:2|:186)
- 4 - B 07 DFFE + 0 2 0 3 |clkdiv:2|clk_count17 (|clkdiv:2|:187)
- 7 - B 01 DFFE + 0 2 0 2 |clkdiv:2|clk_count16 (|clkdiv:2|:188)
- 5 - B 01 DFFE + 0 3 0 3 |clkdiv:2|clk_count15 (|clkdiv:2|:189)
- 2 - B 01 DFFE + 0 2 0 4 |clkdiv:2|clk_count14 (|clkdiv:2|:190)
- 4 - B 08 DFFE + 0 2 0 2 |clkdiv:2|clk_count13 (|clkdiv:2|:191)
- 1 - B 08 DFFE + 0 3 0 3 |clkdiv:2|clk_count12 (|clkdiv:2|:192)
- 5 - B 08 DFFE + 0 2 0 4 |clkdiv:2|clk_count11 (|clkdiv:2|:193)
- 6 - B 07 DFFE + 0 3 0 2 |clkdiv:2|clk_count10 (|clkdiv:2|:194)
- 2 - B 07 DFFE + 0 3 0 3 |clkdiv:2|clk_count9 (|clkdiv:2|:195)
- 3 - B 06 DFFE + 0 2 0 4 |clkdiv:2|clk_count8 (|clkdiv:2|:196)
- 7 - B 06 DFFE + 0 2 0 2 |clkdiv:2|clk_count7 (|clkdiv:2|:197)
- 5 - B 06 DFFE + 0 3 0 2 |clkdiv:2|clk_count6 (|clkdiv:2|:198)
- 4 - B 06 DFFE + 0 2 0 3 |clkdiv:2|clk_count5 (|clkdiv:2|:199)
- 8 - B 04 DFFE + 0 2 0 1 |clkdiv:2|clk_count4 (|clkdiv:2|:200)
- 6 - B 04 DFFE + 0 3 0 1 |clkdiv:2|clk_count3 (|clkdiv:2|:201)
- 7 - B 04 DFFE + 0 2 0 2 |clkdiv:2|clk_count2 (|clkdiv:2|:202)
- 5 - B 04 DFFE + 0 2 0 1 |clkdiv:2|clk_count1 (|clkdiv:2|:203)
- 4 - B 04 DFFE + 0 1 0 2 |clkdiv:2|clk_count0 (|clkdiv:2|:204)
- 6 - B 10 DFFE + 0 4 0 13 |clkdiv:2|:208
- 7 - A 22 AND2 0 2 0 1 |clkscan2:10|lpm_add_sub:168|addcore:adder|:55
- 8 - A 22 AND2 0 3 0 1 |clkscan2:10|lpm_add_sub:168|addcore:adder|:59
- 3 - A 24 OR2 0 3 0 4 |clkscan2:10|lpm_add_sub:169|addcore:adder|:60
- 6 - A 22 OR2 0 4 0 4 |clkscan2:10|:24
- 3 - A 02 DFFE + 0 0 0 13 |clkscan2:10|enable (|clkscan2:10|:52)
- 3 - A 22 DFFE 0 4 0 12 |clkscan2:10|:54
- 1 - A 22 DFFE 0 4 0 13 |clkscan2:10|:55
- 5 - A 22 DFFE 0 4 0 14 |clkscan2:10|:56
- 4 - A 22 DFFE 0 3 0 15 |clkscan2:10|:57
- 5 - A 24 DFFE 0 5 0 5 |clkscan2:10|state2 (|clkscan2:10|:72)
- 2 - A 02 DFFE 0 4 0 6 |clkscan2:10|state1 (|clkscan2:10|:73)
- 4 - A 24 DFFE 0 4 0 8 |clkscan2:10|state0 (|clkscan2:10|:74)
- 8 - A 24 OR2 0 2 0 4 |clkscan2:10|:78
- 2 - A 24 OR2 0 3 0 4 |clkscan2:10|:96
- 1 - A 24 OR2 ! 0 4 0 1 |clkscan2:10|:101
- 8 - A 02 DFFE 0 5 1 0 |clkscan2:10|:156
- 1 - A 02 DFFE 0 5 1 0 |clkscan2:10|:157
- 2 - A 22 DFFE 0 5 1 0 |clkscan2:10|:158
- 6 - A 24 DFFE 0 5 1 0 |clkscan2:10|:159
- 7 - A 24 DFFE 0 5 1 0 |clkscan2:10|:160
- 8 - A 23 DFFE ! 0 3 1 0 |clkscan2:10|:161
- 5 - A 09 OR2 ! 0 4 0 1 |p7segment:3|:144
- 4 - A 09 OR2 s 0 4 0 1 |p7segment:3|~218~1
- 7 - A 09 OR2 s 0 4 0 2 |p7segment:3|~218~2
- 1 - A 09 AND2 ! 0 4 0 7 |p7segment:3|:218
- 6 - A 10 OR2 s 0 4 0 2 |p7segment:3|~227~1
- 7 - A 10 OR2 s 0 4 0 1 |p7segment:3|~227~2
- 1 - A 10 OR2 0 3 1 0 |p7segment:3|:227
- 6 - A 09 OR2 s ! 0 4 0 2 |p7segment:3|~230~1
- 3 - A 09 OR2 0 2 1 0 |p7segment:3|:230
- 2 - A 10 OR2 s 0 2 0 2 |p7segment:3|~233~1
- 4 - A 06 OR2 s 0 4 0 1 |p7segment:3|~233~2
- 8 - A 06 OR2 0 3 1 0 |p7segment:3|:233
- 3 - A 06 OR2 s 0 4 0 1 |p7segment:3|~236~1
- 6 - A 06 OR2 0 2 1 0 |p7segment:3|:236
- 2 - A 06 OR2 s 0 4 0 1 |p7segment:3|~239~1
- 1 - A 06 OR2 0 2 1 0 |p7segment:3|:239
- 3 - A 10 OR2 s 0 4 0 2 |p7segment:3|~242~1
- 2 - A 09 OR2 0 3 1 0 |p7segment:3|:242
- 5 - A 10 OR2 s 0 4 0 1 |p7segment:3|~245~1
- 4 - A 10 OR2 0 3 1 0 |p7segment:3|:245
- 4 - A 02 SOFT s ! 1 0 0 3 reset~1
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\clkscan\clkscan2\clkscan2_top.rpt
clkscan2_top
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 13/ 96( 13%) 5/ 48( 10%) 1/ 48( 2%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 0/ 96( 0%) 22/ 48( 45%) 0/ 48( 0%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
C: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 2/24( 8%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\clkscan\clkscan2\clkscan2_top.rpt
clkscan2_top
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 25 clk
DFF 13 |clkdiv:2|:208
INPUT 1 start
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\clkscan\clkscan2\clkscan2_top.rpt
clkscan2_top
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 12 reset
Device-Specific Information:e:\amj\2003_2004year\course\eda\2004year\2004_experiment\my_design\clkscan\clkscan2\clkscan2_top.rpt
clkscan2_top
** EQUATIONS **
clk : INPUT;
reset : INPUT;
start : INPUT;
-- Node name is 'out0'
-- Equation name is 'out0', type is output
out0 = _LC4_A10;
-- Node name is 'out1'
-- Equation name is 'out1', type is output
out1 = _LC2_A9;
-- Node name is 'out2'
-- Equation name is 'out2', type is output
out2 = _LC1_A6;
-- Node name is 'out3'
-- Equation name is 'out3', type is output
out3 = _LC6_A6;
-- Node name is 'out4'
-- Equation name is 'out4', type is output
out4 = _LC8_A6;
-- Node name is 'out5'
-- Equation name is 'out5', type is output
out5 = _LC3_A9;
-- Node name is 'out6'
-- Equation name is 'out6', type is output
out6 = _LC1_A10;
-- Node name is 'reset~1'
-- Equation name is 'reset~1', location is LC4_A2, type is buried.
-- synthesized logic cell
!_LC4_A2 = _LC4_A2~NOT;
_LC4_A2~NOT = LCELL(!reset);
-- Node name is 'scan_en1'
-- Equation name is 'scan_en1', type is output
scan_en1 = _LC8_A23;
-- Node name is 'scan_en2'
-- Equation name is 'scan_en2', type is output
scan_en2 = _LC7_A24;
-- Node name is 'scan_en3'
-- Equation name is 'scan_en3', type is output
scan_en3 = _LC6_A24;
-- Node name is 'scan_en4'
-- Equation name is 'scan_en4', type is output
scan_en4 = _LC2_A22;
-- Node name is 'scan_en5'
-- Equation name is 'scan_en5', type is output
scan_en5 = _LC1_A2;
-- Node name is 'scan_en6'
-- Equation name is 'scan_en6', type is output
scan_en6 = _LC8_A2;
-- Node name is '|clkdiv:2|:204' = '|clkdiv:2|clk_count0'
-- Equation name is '_LC4_B4', type is buried
_LC4_B4 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = !_LC4_B4 & _LC7_B10;
-- Node name is '|clkdiv:2|:203' = '|clkdiv:2|clk_count1'
-- Equation name is '_LC5_B4', type is buried
_LC5_B4 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC4_B4 & !_LC5_B4 & _LC7_B10
# !_LC4_B4 & _LC5_B4 & _LC7_B10;
-- Node name is '|clkdiv:2|:202' = '|clkdiv:2|clk_count2'
-- Equation name is '_LC7_B4', type is buried
_LC7_B4 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = !_LC1_B4 & _LC7_B4 & _LC7_B10
# _LC1_B4 & !_LC7_B4 & _LC7_B10;
-- Node name is '|clkdiv:2|:201' = '|clkdiv:2|clk_count3'
-- Equation name is '_LC6_B4', type is buried
_LC6_B4 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC6_B4 & !_LC7_B4 & _LC7_B10
# !_LC1_B4 & _LC6_B4 & _LC7_B10
# _LC1_B4 & !_LC6_B4 & _LC7_B4 & _LC7_B10;
-- Node name is '|clkdiv:2|:200' = '|clkdiv:2|clk_count4'
-- Equation name is '_LC8_B4', type is buried
_LC8_B4 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !_LC3_B4 & _LC7_B10 & _LC8_B4
# _LC3_B4 & _LC7_B10 & !_LC8_B4;
-- Node name is '|clkdiv:2|:199' = '|clkdiv:2|clk_count5'
-- Equation name is '_LC4_B6', type is buried
_LC4_B6 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = !_LC2_B4 & _LC4_B6 & _LC7_B10
# _LC2_B4 & !_LC4_B6 & _LC7_B10;
-- Node name is '|clkdiv:2|:198' = '|clkdiv:2|clk_count6'
-- Equation name is '_LC5_B6', type is buried
_LC5_B6 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = !_LC4_B6 & _LC5_B6 & _LC7_B10
# !_LC2_B4 & _LC5_B6 & _LC7_B10
# _LC2_B4 & _LC4_B6 & !_LC5_B6 & _LC7_B10;
-- Node name is '|clkdiv:2|:197' = '|clkdiv:2|clk_count7'
-- Equation name is '_LC7_B6', type is buried
_LC7_B6 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = _LC1_B6 & _LC7_B6 & _LC7_B10
# !_LC1_B6 & !_LC7_B6 & _LC7_B10;
-- Node name is '|clkdiv:2|:196' = '|clkdiv:2|clk_count8'
-- Equation name is '_LC3_B6', type is buried
_LC3_B6 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = _LC3_B6 & _LC7_B10 & !_LC8_B6
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