time2.rpt

来自「此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路」· RPT 代码 · 共 1,289 行 · 第 1/4 页

  _EQ057 =  _LC1_B21 &  _LC5_B7
         #  _LC1_B7 &  _LC2_B21;

-- Node name is ':567' 
-- Equation name is '_LC5_B1', type is buried 
_LC5_B1  = DFFE( _EQ058, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ058 =  _LC1_B21 &  _LC7_B1
         #  _LC2_B21 &  _LC5_B1;

-- Node name is ':568' 
-- Equation name is '_LC4_B1', type is buried 
_LC4_B1  = DFFE( _EQ059, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ059 =  _LC1_B21 &  _LC2_B1
         #  _LC2_B21 &  _LC4_B1;

-- Node name is '~591~1' 
-- Equation name is '~591~1', location is LC3_B6, type is buried.
-- synthesized logic cell 
!_LC3_B6 = _LC3_B6~NOT;
_LC3_B6~NOT = LCELL( _EQ060);
  _EQ060 = !_LC2_B4 & !_LC2_B6 & !_LC3_B11;

-- Node name is '~591~2' 
-- Equation name is '~591~2', location is LC4_B6, type is buried.
-- synthesized logic cell 
!_LC4_B6 = _LC4_B6~NOT;
_LC4_B6~NOT = LCELL( _EQ061);
  _EQ061 = !_LC1_B2 & !_LC1_B6 &  _LC4_B12 & !_LC5_B12;

-- Node name is ':591' 
-- Equation name is '_LC8_B6', type is buried 
_LC8_B6  = LCELL( _EQ062);
  _EQ062 = !_LC3_B6 & !_LC4_B6 &  _LC8_B11 & !reset;

-- Node name is ':621' 
-- Equation name is '_LC1_B12', type is buried 
!_LC1_B12 = _LC1_B12~NOT;
_LC1_B12~NOT = LCELL( _EQ063);
  _EQ063 =  _LC1_B2
         # !_LC2_B12
         # !_LC5_B12
         #  _LC4_B12;

-- Node name is '~738~1' 
-- Equation name is '~738~1', location is LC5_B4, type is buried.
-- synthesized logic cell 
_LC5_B4  = LCELL( _EQ064);
  _EQ064 =  _LC2_B3 & !_LC8_B6;

-- Node name is '~742~1' 
-- Equation name is '~742~1', location is LC8_B12, type is buried.
-- synthesized logic cell 
_LC8_B12 = LCELL( _EQ065);
  _EQ065 = !_LC1_B12 &  _LC5_B4;

-- Node name is '~948~1' 
-- Equation name is '~948~1', location is LC6_B6, type is buried.
-- synthesized logic cell 
_LC6_B6  = LCELL( _EQ066);
  _EQ066 = !_LC2_B6 &  _LC5_B4
         #  _LC1_B11 &  _LC5_B4
         #  _LC6_B4;

-- Node name is '~948~2' 
-- Equation name is '~948~2', location is LC7_B6, type is buried.
-- synthesized logic cell 
_LC7_B6  = LCELL( _EQ067);
  _EQ067 = !_LC1_B6 &  _LC2_B6 &  _LC2_B11
         #  _LC1_B6 &  _LC6_B6;

-- Node name is '~949~1' 
-- Equation name is '~949~1', location is LC1_B11, type is buried.
-- synthesized logic cell 
_LC1_B11 = LCELL( _EQ068);
  _EQ068 = !_LC8_B11
         #  reset
         # !_LC3_B11
         # !_LC1_B12;

-- Node name is '~949~2' 
-- Equation name is '~949~2', location is LC6_B12, type is buried.
-- synthesized logic cell 
_LC6_B12 = LCELL( _EQ069);
  _EQ069 =  _LC1_B11 &  _LC5_B4
         #  _LC6_B4;

-- Node name is '~949~3' 
-- Equation name is '~949~3', location is LC5_B6, type is buried.
-- synthesized logic cell 
_LC5_B6  = LCELL( _EQ070);
  _EQ070 = !_LC2_B6 &  _LC2_B11
         #  _LC2_B6 &  _LC6_B12;

-- Node name is '~950~1' 
-- Equation name is '~950~1', location is LC6_B11, type is buried.
-- synthesized logic cell 
_LC6_B11 = LCELL( _EQ071);
  _EQ071 = !_LC3_B11 &  _LC5_B4
         # !_LC1_B12 &  _LC5_B4
         #  _LC6_B4;

-- Node name is '~950~2' 
-- Equation name is '~950~2', location is LC7_B11, type is buried.
-- synthesized logic cell 
_LC7_B11 = LCELL( _EQ072);
  _EQ072 =  _LC3_B11 &  _LC4_B11 & !_LC8_B11
         #  _LC6_B11 &  _LC8_B11;

-- Node name is '~951~1' 
-- Equation name is '~951~1', location is LC5_B11, type is buried.
-- synthesized logic cell 
_LC5_B11 = LCELL( _EQ073);
  _EQ073 = !_LC3_B11 &  _LC4_B11
         #  _LC3_B11 &  _LC8_B12
         #  _LC3_B11 &  _LC6_B4;

-- Node name is '~952~1' 
-- Equation name is '~952~1', location is LC7_B2, type is buried.
-- synthesized logic cell 
_LC7_B2  = LCELL( _EQ074);
  _EQ074 = !_LC4_B12 &  _LC8_B12
         # !_LC5_B2 &  _LC8_B12
         #  _LC6_B4;

-- Node name is '~952~2' 
-- Equation name is '~952~2', location is LC7_B12, type is buried.
-- synthesized logic cell 
_LC7_B12 = LCELL( _EQ075);
  _EQ075 =  _LC4_B12 & !_LC5_B12 &  _LC8_B2
         #  _LC5_B12 &  _LC7_B2;

-- Node name is '~953~1' 
-- Equation name is '~953~1', location is LC6_B2, type is buried.
-- synthesized logic cell 
_LC6_B2  = LCELL( _EQ076);
  _EQ076 = !_LC5_B2 &  _LC8_B12
         #  _LC6_B4;

-- Node name is '~953~2' 
-- Equation name is '~953~2', location is LC3_B12, type is buried.
-- synthesized logic cell 
_LC3_B12 = LCELL( _EQ077);
  _EQ077 = !_LC4_B12 &  _LC8_B2
         #  _LC4_B12 &  _LC6_B2;

-- Node name is '~954~1' 
-- Equation name is '~954~1', location is LC2_B2, type is buried.
-- synthesized logic cell 
_LC2_B2  = LCELL( _EQ078);
  _EQ078 = !_LC2_B4 &  _LC8_B12
         #  _LC6_B4;

-- Node name is '~954~2' 
-- Equation name is '~954~2', location is LC4_B2, type is buried.
-- synthesized logic cell 
_LC4_B2  = LCELL( _EQ079);
  _EQ079 =  _LC1_B2 &  _LC2_B2
         # !_LC1_B2 &  _LC2_B4 &  _LC3_B2;

-- Node name is '~955~1' 
-- Equation name is '~955~1', location is LC1_B4, type is buried.
-- synthesized logic cell 
_LC1_B4  = LCELL( _EQ080);
  _EQ080 =  _LC2_B4 &  _LC6_B4
         # !_LC2_B4 &  _LC5_B4 & !_LC8_B10;

-- Node name is ':956' 
-- Equation name is '_LC1_B6', type is buried 
_LC1_B6  = DFFE( _EQ081, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ081 =  _LC1_B21 &  _LC7_B6
         #  _LC1_B6 &  _LC2_B21;

-- Node name is ':957' 
-- Equation name is '_LC2_B6', type is buried 
_LC2_B6  = DFFE( _EQ082, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ082 =  _LC1_B21 &  _LC5_B6
         #  _LC2_B6 &  _LC2_B21;

-- Node name is ':958' 
-- Equation name is '_LC8_B11', type is buried 
_LC8_B11 = DFFE( _EQ083, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ083 =  _LC1_B21 &  _LC7_B11
         #  _LC2_B21 &  _LC8_B11;

-- Node name is ':959' 
-- Equation name is '_LC3_B11', type is buried 
_LC3_B11 = DFFE( _EQ084, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ084 =  _LC1_B21 &  _LC5_B11
         #  _LC2_B21 &  _LC3_B11;

-- Node name is ':960' 
-- Equation name is '_LC5_B12', type is buried 
_LC5_B12 = DFFE( _EQ085, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ085 =  _LC1_B21 &  _LC7_B12
         #  _LC2_B21 &  _LC5_B12;

-- Node name is ':961' 
-- Equation name is '_LC4_B12', type is buried 
_LC4_B12 = DFFE( _EQ086, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ086 =  _LC1_B21 &  _LC3_B12
         #  _LC2_B21 &  _LC4_B12;

-- Node name is ':962' 
-- Equation name is '_LC1_B2', type is buried 
_LC1_B2  = DFFE( _EQ087, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ087 =  _LC1_B21 &  _LC4_B2
         #  _LC1_B2 &  _LC2_B21;

-- Node name is ':963' 
-- Equation name is '_LC2_B4', type is buried 
_LC2_B4  = DFFE( _EQ088, GLOBAL( clk),  VCC,  VCC,  VCC);
  _EQ088 =  _LC1_B4 &  _LC1_B21
         #  _LC2_B4 &  _LC2_B21;

-- Node name is '~982~1' 
-- Equation name is '~982~1', location is LC6_B4, type is buried.
-- synthesized logic cell 
_LC6_B4  = LCELL( _EQ089);
  _EQ089 = !_LC2_B3
         #  _LC8_B10;

-- Node name is ':987' 
-- Equation name is '_LC3_B4', type is buried 
_LC3_B4  = DFFE( _EQ090, GLOBAL( clk),  VCC,  VCC,  _LC1_B21);
  _EQ090 = !_LC6_B4 &  _LC8_B6
         #  _LC3_B4 &  _LC6_B4;



Project Information      e:\amj\eda\2003\experiment\clkscan\clkscan3\time2.rpt

** COMPILATION SETTINGS & TIMES **

Processing Menu Commands
------------------------

Design Doctor                             = off

Logic Synthesis:

   Synthesis Type Used                    = Multi-Level

   Default Synthesis Style                = NORMAL

      Logic option settings in 'NORMAL' style for 'FLEX10K' family

      CARRY_CHAIN                         = ignore
      CARRY_CHAIN_LENGTH                  = 32
      CASCADE_CHAIN                       = ignore
      CASCADE_CHAIN_LENGTH                = 2
      DECOMPOSE_GATES                     = on
      DUPLICATE_LOGIC_EXTRACTION          = on
      MINIMIZATION                        = full
      MULTI_LEVEL_FACTORING               = on
      NOT_GATE_PUSH_BACK                  = on
      REDUCE_LOGIC                        = on
      REFACTORIZATION                     = on
      REGISTER_OPTIMIZATION               = on
      RESYNTHESIZE_NETWORK                = on
      SLOW_SLEW_RATE                      = off
      SUBFACTOR_EXTRACTION                = on
      IGNORE_SOFT_BUFFERS                 = on
      USE_LPM_FOR_AHDL_OPERATORS          = off

   Other logic synthesis settings:

      Automatic Global Clock              = on
      Automatic Global Clear              = on
      Automatic Global Preset             = on
      Automatic Global Output Enable      = on
      Automatic Fast I/O                  = off
      Automatic Register Packing          = off
      Automatic Open-Drain Pins           = on
      Automatic Implement in EAB          = off
      Optimize                            = 5

Default Timing Specifications: None

Cut All Bidir Feedback Timing Paths       = on
Cut All Clear & Preset Timing Paths       = on

Ignore Timing Assignments                 = off

Functional SNF Extractor                  = off

Linked SNF Extractor                      = off
Timing SNF Extractor                      = on
Optimize Timing SNF                       = off
Generate AHDL TDO File                    = off
Fitter Settings                           = NORMAL
Use Quartus Fitter                        = on
Smart Recompile                           = off
Total Recompile                           = off

Interfaces Menu Commands
------------------------

EDIF Netlist Writer                       = off
Verilog Netlist Writer                    = off
VHDL Netlist Writer                       = off

Compilation Times
-----------------

   Compiler Netlist Extractor             00:00:00
   Database Builder                       00:00:00
   Logic Synthesizer                      00:00:00
   Partitioner                            00:00:01
   Fitter                                 00:00:02
   Timing SNF Extractor                   00:00:00
   Assembler                              00:00:00
   --------------------------             --------
   Total Time                             00:00:03


Memory Allocated
-----------------

Peak memory allocated during compilation  = 15,298K