time2.rpt
来自「此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路」· RPT 代码 · 共 1,289 行 · 第 1/4 页
RPT
1,289 行
- 2 - B 12 OR2 s ! 1 1 0 1 |lpm_add_sub:994|addcore:adder|~55~1
- 5 - B 02 OR2 ! 1 2 0 3 |lpm_add_sub:994|addcore:adder|:55
- 3 - B 21 DFFE + 1 0 0 2 started (:34)
- 3 - B 02 AND2 s 0 2 0 1 ~38~1
- 8 - B 02 AND2 s 0 3 0 2 ~38~2
- 4 - B 11 AND2 s 0 3 0 3 ~38~3
- 2 - B 11 AND2 s 1 3 0 2 ~38~4
- 2 - B 10 AND2 s 0 4 0 2 ~38~5
- 1 - B 21 OR2 2 1 0 23 :38
- 3 - B 14 OR2 ! 0 4 0 12 :59
- 5 - B 19 OR2 ! 0 4 0 11 :91
- 7 - B 19 OR2 0 4 0 1 :198
- 4 - B 19 OR2 0 4 0 1 :199
- 3 - B 10 OR2 0 4 0 1 :200
- 6 - B 14 AND2 s 0 2 0 3 ~210~1
- 2 - B 21 AND2 s 2 1 0 24 ~236~1
- 1 - B 19 DFFE + 0 3 1 2 :252
- 8 - B 19 DFFE + 0 3 1 3 :253
- 7 - B 10 DFFE + 0 3 1 4 :254
- 6 - B 10 DFFE + 0 3 1 4 :255
- 2 - B 14 DFFE + 0 3 1 1 :256
- 1 - B 14 DFFE + 0 3 1 2 :257
- 4 - B 14 DFFE + 0 3 1 3 :258
- 5 - B 10 DFFE + 0 2 1 4 :259
- 8 - B 07 OR2 ! 0 4 0 6 :282
- 2 - B 03 OR2 ! 0 4 0 6 :314
- 5 - B 03 OR2 0 4 0 1 :421
- 4 - B 07 AND2 s 0 2 0 3 ~433~1
- 6 - B 07 OR2 0 4 0 1 :433
- 2 - B 07 OR2 0 4 0 1 :469
- 3 - B 01 OR2 0 4 0 1 :470
- 8 - B 01 OR2 0 4 0 1 :507
- 7 - B 07 OR2 0 4 0 1 :511
- 5 - B 07 OR2 0 3 0 1 :512
- 7 - B 01 OR2 0 3 0 1 :513
- 2 - B 01 OR2 0 3 0 1 :514
- 6 - B 03 OR2 s 0 4 0 1 ~554~1
- 7 - B 03 OR2 s 0 4 0 1 ~554~2
- 7 - B 04 OR2 s 0 4 0 1 ~555~1
- 8 - B 04 OR2 s 0 4 0 1 ~555~2
- 8 - B 10 OR2 s 0 3 0 8 ~556~1
- 6 - B 01 DFFE + 0 3 1 3 :561
- 3 - B 03 DFFE + 0 3 1 3 :562
- 4 - B 04 DFFE + 0 3 1 4 :563
- 1 - B 10 DFFE + 0 3 1 5 :564
- 3 - B 07 DFFE + 0 3 1 3 :565
- 1 - B 07 DFFE + 0 3 1 4 :566
- 5 - B 01 DFFE + 0 3 1 4 :567
- 4 - B 01 DFFE + 0 3 1 4 :568
- 3 - B 06 AND2 s ! 0 3 0 1 ~591~1
- 4 - B 06 AND2 s ! 0 4 0 1 ~591~2
- 8 - B 06 AND2 1 3 0 2 :591
- 1 - B 12 OR2 ! 0 4 0 4 :621
- 5 - B 04 AND2 s 0 2 0 6 ~738~1
- 8 - B 12 AND2 s 0 2 0 6 ~742~1
- 6 - B 06 OR2 s 0 4 0 1 ~948~1
- 7 - B 06 OR2 s 0 4 0 1 ~948~2
- 1 - B 11 OR2 s 1 3 0 2 ~949~1
- 6 - B 12 OR2 s 0 3 0 1 ~949~2
- 5 - B 06 OR2 s 0 3 0 1 ~949~3
- 6 - B 11 OR2 s 0 4 0 1 ~950~1
- 7 - B 11 OR2 s 0 4 0 1 ~950~2
- 5 - B 11 OR2 s 0 4 0 1 ~951~1
- 7 - B 02 OR2 s 0 4 0 1 ~952~1
- 7 - B 12 OR2 s 0 4 0 1 ~952~2
- 6 - B 02 OR2 s 0 3 0 1 ~953~1
- 3 - B 12 OR2 s 0 3 0 1 ~953~2
- 2 - B 02 OR2 s 0 3 0 1 ~954~1
- 4 - B 02 OR2 s 0 4 0 1 ~954~2
- 1 - B 04 OR2 s 0 4 0 1 ~955~1
- 1 - B 06 DFFE + 0 3 1 2 :956
- 2 - B 06 DFFE + 0 3 1 4 :957
- 8 - B 11 DFFE + 0 3 1 4 :958
- 3 - B 11 DFFE + 0 3 1 6 :959
- 5 - B 12 DFFE + 0 3 1 3 :960
- 4 - B 12 DFFE + 0 3 1 5 :961
- 1 - B 02 DFFE + 0 3 1 4 :962
- 2 - B 04 DFFE + 0 3 1 6 :963
- 6 - B 04 OR2 s 0 2 0 9 ~982~1
- 3 - B 04 DFFE + 0 3 1 0 :987
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\time2.rpt
time2
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 0/ 96( 0%) 0/ 48( 0%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
B: 14/ 96( 14%) 31/ 48( 64%) 1/ 48( 2%) 0/16( 0%) 9/16( 56%) 0/16( 0%)
C: 0/ 96( 0%) 2/ 48( 4%) 0/ 48( 0%) 0/16( 0%) 2/16( 12%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
02: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
03: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
04: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
05: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
07: 2/24( 8%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
12: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
13: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
14: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
20: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
23: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
24: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\time2.rpt
time2
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 26 clk
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\time2.rpt
time2
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 19 reset
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\time2.rpt
time2
** EQUATIONS **
clk : INPUT;
reset : INPUT;
start : INPUT;
-- Node name is 'day'
-- Equation name is 'day', type is output
day = _LC3_B4;
-- Node name is 'hour0'
-- Equation name is 'hour0', type is output
hour0 = _LC2_B4;
-- Node name is 'hour1'
-- Equation name is 'hour1', type is output
hour1 = _LC1_B2;
-- Node name is 'hour2'
-- Equation name is 'hour2', type is output
hour2 = _LC4_B12;
-- Node name is 'hour3'
-- Equation name is 'hour3', type is output
hour3 = _LC5_B12;
-- Node name is 'hour4'
-- Equation name is 'hour4', type is output
hour4 = _LC3_B11;
-- Node name is 'hour5'
-- Equation name is 'hour5', type is output
hour5 = _LC8_B11;
-- Node name is 'hour6'
-- Equation name is 'hour6', type is output
hour6 = _LC2_B6;
-- Node name is 'hour7'
-- Equation name is 'hour7', type is output
hour7 = _LC1_B6;
-- Node name is 'min0'
-- Equation name is 'min0', type is output
min0 = _LC4_B1;
-- Node name is 'min1'
-- Equation name is 'min1', type is output
min1 = _LC5_B1;
-- Node name is 'min2'
-- Equation name is 'min2', type is output
min2 = _LC1_B7;
-- Node name is 'min3'
-- Equation name is 'min3', type is output
min3 = _LC3_B7;
-- Node name is 'min4'
-- Equation name is 'min4', type is output
min4 = _LC1_B10;
-- Node name is 'min5'
-- Equation name is 'min5', type is output
min5 = _LC4_B4;
-- Node name is 'min6'
-- Equation name is 'min6', type is output
min6 = _LC3_B3;
-- Node name is 'min7'
-- Equation name is 'min7', type is output
min7 = _LC6_B1;
-- Node name is 'sec0'
-- Equation name is 'sec0', type is output
sec0 = _LC5_B10;
-- Node name is 'sec1'
-- Equation name is 'sec1', type is output
sec1 = _LC4_B14;
-- Node name is 'sec2'
-- Equation name is 'sec2', type is output
sec2 = _LC1_B14;
-- Node name is 'sec3'
-- Equation name is 'sec3', type is output
sec3 = _LC2_B14;
-- Node name is 'sec4'
-- Equation name is 'sec4', type is output
sec4 = _LC6_B10;
-- Node name is 'sec5'
-- Equation name is 'sec5', type is output
sec5 = _LC7_B10;
-- Node name is 'sec6'
-- Equation name is 'sec6', type is output
sec6 = _LC8_B19;
-- Node name is 'sec7'
-- Equation name is 'sec7', type is output
sec7 = _LC1_B19;
-- Node name is ':34' = 'started'
-- Equation name is 'started', location is LC3_B21, type is buried.
started = DFFE( VCC, GLOBAL( clk), GLOBAL(!reset), GLOBAL(!start), start);
-- Node name is '|lpm_add_sub:989|addcore:adder|~55~1' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC2_B19', type is buried
-- synthesized logic cell
!_LC2_B19 = _LC2_B19~NOT;
_LC2_B19~NOT = LCELL( _EQ001);
_EQ001 = !_LC6_B10
# reset;
-- Node name is '|lpm_add_sub:989|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC3_B19', type is buried
_LC3_B19 = LCELL( _EQ002);
_EQ002 = _LC6_B10 & _LC7_B10 & !reset;
-- Node name is '|lpm_add_sub:989|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC6_B19', type is buried
_LC6_B19 = LCELL( _EQ003);
_EQ003 = _LC6_B10 & _LC7_B10 & _LC8_B19 & !reset;
-- Node name is '|lpm_add_sub:990|addcore:adder|~55~1' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC5_B14', type is buried
-- synthesized logic cell
!_LC5_B14 = _LC5_B14~NOT;
_LC5_B14~NOT = LCELL( _EQ004);
_EQ004 = !_LC5_B10
# reset;
-- Node name is '|lpm_add_sub:990|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC7_B14', type is buried
_LC7_B14 = LCELL( _EQ005);
_EQ005 = _LC4_B14 & _LC5_B10 & !reset;
-- Node name is '|lpm_add_sub:990|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B14', type is buried
_LC8_B14 = LCELL( _EQ006);
_EQ006 = _LC1_B14 & _LC4_B14 & _LC5_B10 & !reset;
-- Node name is '|lpm_add_sub:991|addcore:adder|~55~1' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC1_B3', type is buried
-- synthesized logic cell
!_LC1_B3 = _LC1_B3~NOT;
_LC1_B3~NOT = LCELL( _EQ007);
_EQ007 = !_LC1_B10
# reset;
-- Node name is '|lpm_add_sub:991|addcore:adder|:55' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC4_B3', type is buried
_LC4_B3 = LCELL( _EQ008);
_EQ008 = _LC1_B10 & _LC4_B4 & !reset;
-- Node name is '|lpm_add_sub:991|addcore:adder|:59' from file "addcore.tdf" line 312, column 64
-- Equation name is '_LC8_B3', type is buried
_LC8_B3 = LCELL( _EQ009);
_EQ009 = _LC1_B10 & _LC3_B3 & _LC4_B4 & !reset;
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