clkscan3_top.rpt
来自「此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路」· RPT 代码 · 共 1,275 行 · 第 1/5 页
RPT
1,275 行
- 5 - B 08 AND2 0 3 0 1 |timer:15|lpm_add_sub:303|addcore:adder|:59
- 8 - B 05 AND2 0 2 0 1 |timer:15|lpm_add_sub:304|addcore:adder|:55
- 1 - B 12 DFFE 1 1 0 12 |timer:15|started (|timer:15|:30)
- 1 - B 13 OR2 s ! 0 4 0 5 |timer:15|~32~1
- 1 - B 17 OR2 ! 0 4 0 10 |timer:15|:69
- 7 - B 13 OR2 1 3 0 1 |timer:15|:92
- 2 - B 13 OR2 1 3 0 1 |timer:15|:93
- 7 - B 23 OR2 1 3 0 1 |timer:15|:94
- 6 - B 23 AND2 s 0 4 0 1 |timer:15|~116~1
- 8 - B 13 OR2 0 4 0 1 |timer:15|:116
- 3 - B 13 OR2 0 4 0 1 |timer:15|:117
- 8 - B 23 OR2 0 4 0 1 |timer:15|:118
- 3 - B 17 AND2 s 0 2 0 3 |timer:15|~120~1
- 1 - B 21 AND2 s 1 1 0 3 |timer:15|~129~1
- 5 - B 23 OR2 s 0 2 0 1 |timer:15|~136~1
- 5 - B 13 DFFE 1 3 0 3 |timer:15|:141
- 4 - B 13 DFFE 1 3 0 4 |timer:15|:142
- 2 - B 23 DFFE 1 3 0 5 |timer:15|:143
- 1 - B 23 DFFE 1 3 0 6 |timer:15|:144
- 5 - B 17 DFFE 0 4 0 2 |timer:15|:145
- 8 - B 17 DFFE 0 4 0 3 |timer:15|:146
- 4 - B 17 DFFE 0 4 0 4 |timer:15|:147
- 6 - B 17 DFFE 1 2 0 5 |timer:15|:148
- 4 - B 23 DFFE 0 4 0 9 |timer:15|min_clk (|timer:15|:153)
- 6 - B 18 OR2 s ! 0 4 0 4 |timer:15|~155~1
- 1 - B 18 AND2 s 0 3 0 1 |timer:15|~155~2
- 1 - B 14 OR2 ! 0 4 0 7 |timer:15|:167
- 8 - B 18 DFFE 0 4 0 3 |timer:15|:214
- 2 - B 18 DFFE 0 4 0 4 |timer:15|:215
- 3 - B 18 DFFE 0 4 0 5 |timer:15|:216
- 5 - B 18 DFFE 0 3 0 6 |timer:15|:217
- 8 - B 14 DFFE 0 4 0 2 |timer:15|:218
- 3 - B 14 DFFE 0 4 0 3 |timer:15|:219
- 6 - B 14 DFFE 0 3 0 4 |timer:15|:220
- 5 - B 14 DFFE 0 1 0 5 |timer:15|:221
- 7 - B 14 DFFE 0 5 0 8 |timer:15|h_clk (|timer:15|:225)
- 2 - B 08 OR2 s 0 3 0 1 |timer:15|~227~1
- 1 - B 08 OR2 s 0 3 0 1 |timer:15|~227~2
- 3 - B 05 OR2 ! 0 4 0 7 |timer:15|:227
- 4 - B 05 OR2 ! 0 4 0 6 |timer:15|:239
- 7 - B 05 AND2 s 0 2 0 2 |timer:15|~274~1
- 7 - B 08 DFFE 0 4 0 2 |timer:15|:286
- 6 - B 08 DFFE 0 4 0 3 |timer:15|:287
- 3 - B 08 DFFE 0 4 0 4 |timer:15|:288
- 8 - B 08 DFFE 0 3 0 5 |timer:15|:289
- 1 - B 05 DFFE 0 4 0 3 |timer:15|:290
- 2 - B 05 DFFE 0 4 0 4 |timer:15|:291
- 5 - B 05 DFFE 0 4 0 5 |timer:15|:292
- 6 - B 05 DFFE 0 2 0 6 |timer:15|:293
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
p = Packed register
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\clkscan3_top.rpt
clkscan3_top
** FASTTRACK INTERCONNECT UTILIZATION **
Row FastTrack Interconnect:
Global Left Half- Right Half-
FastTrack FastTrack FastTrack
Row Interconnect Interconnect Interconnect Input Pins Output Pins Bidir Pins
A: 1/ 96( 1%) 25/ 48( 52%) 0/ 48( 0%) 0/16( 0%) 4/16( 25%) 0/16( 0%)
B: 31/ 96( 32%) 16/ 48( 33%) 20/ 48( 41%) 0/16( 0%) 3/16( 18%) 0/16( 0%)
C: 0/ 96( 0%) 10/ 48( 20%) 0/ 48( 0%) 0/16( 0%) 0/16( 0%) 0/16( 0%)
Column FastTrack Interconnect:
FastTrack
Column Interconnect Input Pins Output Pins Bidir Pins
01: 3/24( 12%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
02: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
03: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
04: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
05: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
06: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
07: 4/24( 16%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
08: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
09: 1/24( 4%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
10: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
11: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
12: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
13: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
14: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
15: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
16: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
17: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
18: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
19: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
20: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
21: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
22: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
23: 1/24( 4%) 0/4( 0%) 1/4( 25%) 0/4( 0%)
24: 2/24( 8%) 0/4( 0%) 2/4( 50%) 0/4( 0%)
EA: 0/24( 0%) 0/4( 0%) 0/4( 0%) 0/4( 0%)
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\clkscan3_top.rpt
clkscan3_top
** CLOCK SIGNALS **
Type Fan-out Name
INPUT 40 clk
DFF 13 |clkdiv2:11|:136
DFF 10 |clkdiv:5|:200
DFF 9 |timer:15|min_clk
DFF 8 |timer:15|h_clk
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\clkscan3_top.rpt
clkscan3_top
** CLEAR SIGNALS **
Type Fan-out Name
INPUT 27 reset
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\clkscan3_top.rpt
clkscan3_top
** EQUATIONS **
clk : INPUT;
reset : INPUT;
start : INPUT;
-- Node name is 'out0'
-- Equation name is 'out0', type is output
out0 = _LC4_B7;
-- Node name is 'out1'
-- Equation name is 'out1', type is output
out1 = _LC2_B7;
-- Node name is 'out2'
-- Equation name is 'out2', type is output
out2 = _LC1_B3;
-- Node name is 'out3'
-- Equation name is 'out3', type is output
out3 = _LC6_B2;
-- Node name is 'out4'
-- Equation name is 'out4', type is output
out4 = _LC5_B7;
-- Node name is 'out5'
-- Equation name is 'out5', type is output
out5 = _LC3_B7;
-- Node name is 'out6'
-- Equation name is 'out6', type is output
out6 = _LC1_B7;
-- Node name is 'reset~1'
-- Equation name is 'reset~1', location is LC1_B16, type is buried.
-- synthesized logic cell
!_LC1_B16 = _LC1_B16~NOT;
_LC1_B16~NOT = LCELL(!reset);
-- Node name is 'scan_en1'
-- Equation name is 'scan_en1', type is output
scan_en1 = _LC3_B24;
-- Node name is 'scan_en2'
-- Equation name is 'scan_en2', type is output
scan_en2 = _LC1_B24;
-- Node name is 'scan_en3'
-- Equation name is 'scan_en3', type is output
scan_en3 = _LC7_B24;
-- Node name is 'scan_en4'
-- Equation name is 'scan_en4', type is output
scan_en4 = _LC8_B22;
-- Node name is 'scan_en5'
-- Equation name is 'scan_en5', type is output
scan_en5 = _LC1_B1;
-- Node name is 'scan_en6'
-- Equation name is 'scan_en6', type is output
scan_en6 = _LC6_B1;
-- Node name is '|clkdiv2:11|:132' = '|clkdiv2:11|clk_count0'
-- Equation name is '_LC3_C5', type is buried
_LC3_C5 = DFFE( _EQ001, GLOBAL( clk), VCC, VCC, VCC);
_EQ001 = _LC1_C8 & !_LC3_C5;
-- Node name is '|clkdiv2:11|:131' = '|clkdiv2:11|clk_count1'
-- Equation name is '_LC4_C5', type is buried
_LC4_C5 = DFFE( _EQ002, GLOBAL( clk), VCC, VCC, VCC);
_EQ002 = _LC1_C8 & _LC3_C5 & !_LC4_C5
# _LC1_C8 & !_LC3_C5 & _LC4_C5;
-- Node name is '|clkdiv2:11|:130' = '|clkdiv2:11|clk_count2'
-- Equation name is '_LC6_C5', type is buried
_LC6_C5 = DFFE( _EQ003, GLOBAL( clk), VCC, VCC, VCC);
_EQ003 = _LC1_C8 & !_LC2_C5 & _LC6_C5
# _LC1_C8 & _LC2_C5 & !_LC6_C5;
-- Node name is '|clkdiv2:11|:129' = '|clkdiv2:11|clk_count3'
-- Equation name is '_LC5_C5', type is buried
_LC5_C5 = DFFE( _EQ004, GLOBAL( clk), VCC, VCC, VCC);
_EQ004 = _LC1_C8 & _LC5_C5 & !_LC6_C5
# _LC1_C8 & !_LC2_C5 & _LC5_C5
# _LC1_C8 & _LC2_C5 & !_LC5_C5 & _LC6_C5;
-- Node name is '|clkdiv2:11|:128' = '|clkdiv2:11|clk_count4'
-- Equation name is '_LC4_C2', type is buried
_LC4_C2 = DFFE( _EQ005, GLOBAL( clk), VCC, VCC, VCC);
_EQ005 = !_LC1_C5 & _LC1_C8 & _LC4_C2
# _LC1_C5 & _LC1_C8 & !_LC4_C2;
-- Node name is '|clkdiv2:11|:127' = '|clkdiv2:11|clk_count5'
-- Equation name is '_LC5_C2', type is buried
_LC5_C2 = DFFE( _EQ006, GLOBAL( clk), VCC, VCC, VCC);
_EQ006 = _LC1_C2 & _LC1_C8 & _LC5_C2
# !_LC1_C2 & _LC1_C8 & !_LC5_C2;
-- Node name is '|clkdiv2:11|:126' = '|clkdiv2:11|clk_count6'
-- Equation name is '_LC6_C2', type is buried
_LC6_C2 = DFFE( _EQ007, GLOBAL( clk), VCC, VCC, VCC);
_EQ007 = _LC1_C8 & !_LC5_C2 & _LC6_C2
# _LC1_C2 & _LC1_C8 & _LC6_C2
# !_LC1_C2 & _LC1_C8 & _LC5_C2 & !_LC6_C2;
-- Node name is '|clkdiv2:11|:125' = '|clkdiv2:11|clk_count7'
-- Equation name is '_LC3_C6', type is buried
_LC3_C6 = DFFE( _EQ008, GLOBAL( clk), VCC, VCC, VCC);
_EQ008 = _LC1_C8 & !_LC2_C2 & _LC3_C6
# _LC1_C8 & _LC2_C2 & !_LC3_C6;
-- Node name is '|clkdiv2:11|:124' = '|clkdiv2:11|clk_count8'
-- Equation name is '_LC8_C6', type is buried
_LC8_C6 = DFFE( _EQ009, GLOBAL( clk), VCC, VCC, VCC);
_EQ009 = _LC1_C8 & !_LC3_C6 & _LC8_C6
# _LC1_C8 & !_LC2_C2 & _LC8_C6
# _LC1_C8 & _LC2_C2 & _LC3_C6 & !_LC8_C6;
-- Node name is '|clkdiv2:11|:123' = '|clkdiv2:11|clk_count9'
-- Equation name is '_LC7_C6', type is buried
_LC7_C6 = DFFE( _EQ010, GLOBAL( clk), VCC, VCC, VCC);
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