clkscan3_top.rpt
来自「此设计采用Verilog HDL硬件语言设计,在掌宇开发板上实现. 将整个电路」· RPT 代码 · 共 1,275 行 · 第 1/5 页
RPT
1,275 行
Array Embedded Interconnect Interconnect Read/ External
Block Cells Driven Driven Clocks Write Interconnect
Total dedicated input pins used: 3/6 ( 50%)
Total I/O pins used: 13/53 ( 24%)
Total logic cells used: 194/576 ( 33%)
Total embedded cells used: 0/24 ( 0%)
Total EABs used: 0/3 ( 0%)
Average fan-in: 3.37/4 ( 84%)
Total fan-in: 655/2304 ( 28%)
Total input pins required: 3
Total input I/O cell registers required: 0
Total output pins required: 13
Total output I/O cell registers required: 0
Total buried I/O cell registers required: 0
Total bidirectional pins required: 0
Total reserved pins required 0
Total logic cells required: 194
Total flipflops required: 80
Total packed registers required: 0
Total logic cells in carry chains: 0
Total number of carry chains: 0
Total logic cells in cascade chains: 0
Total number of cascade chains: 0
Total single-pin Clock Enables required: 0
Total single-pin Output Enables required: 0
Synthesized logic cells: 42/ 576 ( 7%)
Logic Cell and Embedded Cell Counts
Column: 01 02 03 04 05 06 07 08 09 10 11 12 EA 13 14 15 16 17 18 19 20 21 22 23 24 Total(LC/EC)
A: 8 0 2 8 7 0 0 2 0 8 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 43/0
B: 7 8 8 0 8 0 8 8 0 0 3 1 0 8 8 6 1 8 8 8 5 1 8 8 3 123/0
C: 0 6 0 0 6 8 0 8 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 28/0
Total: 15 14 10 8 21 8 8 18 0 8 11 1 0 8 8 6 1 8 8 8 5 1 8 8 3 194/0
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\clkscan3_top.rpt
clkscan3_top
** INPUTS **
Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
1 - - - -- INPUT G 0 0 0 0 clk
84 - - - -- INPUT G 0 0 0 10 reset
44 - - - -- INPUT G 0 0 0 1 start
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
G = Global Source. Fan-out destinations counted here do not include destinations
that are driven using global routing resources. Refer to the Auto Global Signals,
Clock Signals, Clear Signals, Synchronous Load Signals, and Synchronous Clear Signals
Sections of this Report File for information on which signals' fan-outs are used as
Clock, Clear, Preset, Output Enable, and synchronous Load signals.
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\clkscan3_top.rpt
clkscan3_top
** OUTPUTS **
Fed By Fed By Fan-In Fan-Out
Pin LC EC Row Col Primitive Code INP FBK OUT FBK Name
23 - - B -- OUTPUT 0 1 0 0 out0
22 - - B -- OUTPUT 0 1 0 0 out1
21 - - B -- OUTPUT 0 1 0 0 out2
19 - - A -- OUTPUT 0 1 0 0 out3
18 - - A -- OUTPUT 0 1 0 0 out4
17 - - A -- OUTPUT 0 1 0 0 out5
16 - - A -- OUTPUT 0 1 0 0 out6
78 - - - 24 OUTPUT 0 1 0 0 scan_en1
79 - - - 24 OUTPUT 0 1 0 0 scan_en2
80 - - - 23 OUTPUT 0 1 0 0 scan_en3
81 - - - 22 OUTPUT 0 1 0 0 scan_en4
10 - - - 01 OUTPUT 0 1 0 0 scan_en5
11 - - - 01 OUTPUT 0 1 0 0 scan_en6
Code:
s = Synthesized pin or logic cell
+ = Synchronous flipflop
/ = Slow slew-rate output
! = NOT gate push-back
r = Fitter-inserted logic cell
@ = Uses single-pin Clock Enable
& = Uses single-pin Output Enable
Device-Specific Information:e:\amj\eda\2003\experiment\clkscan\clkscan3\clkscan3_top.rpt
clkscan3_top
** BURIED LOGIC **
Fan-In Fan-Out
IOC LC EC Row Col Primitive Code INP FBK OUT FBK Name
- 2 - C 05 OR2 ! 0 2 0 3 |clkdiv2:11|lpm_add_sub:137|addcore:adder|:99
- 1 - C 05 OR2 ! 0 3 0 3 |clkdiv2:11|lpm_add_sub:137|addcore:adder|:107
- 2 - C 02 AND2 0 4 0 4 |clkdiv2:11|lpm_add_sub:137|addcore:adder|:119
- 6 - C 06 AND2 0 3 0 1 |clkdiv2:11|lpm_add_sub:137|addcore:adder|:127
- 2 - C 06 AND2 0 4 0 4 |clkdiv2:11|lpm_add_sub:137|addcore:adder|:131
- 4 - C 08 AND2 0 3 0 1 |clkdiv2:11|lpm_add_sub:137|addcore:adder|:139
- 2 - C 08 AND2 0 4 0 2 |clkdiv2:11|lpm_add_sub:137|addcore:adder|:143
- 1 - C 08 OR2 0 4 0 15 |clkdiv2:11|:12
- 5 - C 06 OR2 s 0 3 0 1 |clkdiv2:11|~27~1
- 1 - C 06 OR2 0 4 0 2 |clkdiv2:11|:27
- 3 - C 02 AND2 s 0 3 0 1 |clkdiv2:11|~39~1
- 1 - C 02 OR2 0 2 0 3 |clkdiv2:11|:62
- 7 - C 08 DFFE + 0 3 0 2 |clkdiv2:11|clk_count14 (|clkdiv2:11|:118)
- 3 - C 08 DFFE + 0 2 0 3 |clkdiv2:11|clk_count13 (|clkdiv2:11|:119)
- 5 - C 08 DFFE + 0 2 0 3 |clkdiv2:11|clk_count12 (|clkdiv2:11|:120)
- 8 - C 08 DFFE + 0 3 0 3 |clkdiv2:11|clk_count11 (|clkdiv2:11|:121)
- 4 - C 06 DFFE + 0 2 0 4 |clkdiv2:11|clk_count10 (|clkdiv2:11|:122)
- 7 - C 06 DFFE + 0 2 0 2 |clkdiv2:11|clk_count9 (|clkdiv2:11|:123)
- 8 - C 06 DFFE + 0 3 0 3 |clkdiv2:11|clk_count8 (|clkdiv2:11|:124)
- 3 - C 06 DFFE + 0 2 0 4 |clkdiv2:11|clk_count7 (|clkdiv2:11|:125)
- 6 - C 02 DFFE + 0 3 0 2 |clkdiv2:11|clk_count6 (|clkdiv2:11|:126)
- 5 - C 02 DFFE + 0 2 0 3 |clkdiv2:11|clk_count5 (|clkdiv2:11|:127)
- 4 - C 02 DFFE + 0 2 0 2 |clkdiv2:11|clk_count4 (|clkdiv2:11|:128)
- 5 - C 05 DFFE + 0 3 0 1 |clkdiv2:11|clk_count3 (|clkdiv2:11|:129)
- 6 - C 05 DFFE + 0 2 0 2 |clkdiv2:11|clk_count2 (|clkdiv2:11|:130)
- 4 - C 05 DFFE + 0 2 0 1 |clkdiv2:11|clk_count1 (|clkdiv2:11|:131)
- 3 - C 05 DFFE + 0 1 0 2 |clkdiv2:11|clk_count0 (|clkdiv2:11|:132)
- 6 - C 08 DFFE + 0 4 0 13 |clkdiv2:11|:136
- 1 - A 01 OR2 ! 0 3 0 2 |clkdiv:5|lpm_add_sub:201|addcore:adder|:135
- 8 - A 01 OR2 ! 0 2 0 4 |clkdiv:5|lpm_add_sub:201|addcore:adder|:139
- 2 - A 04 AND2 0 4 0 4 |clkdiv:5|lpm_add_sub:201|addcore:adder|:151
- 2 - A 03 AND2 0 2 0 1 |clkdiv:5|lpm_add_sub:201|addcore:adder|:155
- 6 - A 04 AND2 0 4 0 4 |clkdiv:5|lpm_add_sub:201|addcore:adder|:163
- 8 - A 11 AND2 0 3 0 1 |clkdiv:5|lpm_add_sub:201|addcore:adder|:171
- 2 - A 11 AND2 0 4 0 4 |clkdiv:5|lpm_add_sub:201|addcore:adder|:175
- 5 - A 05 AND2 0 3 0 1 |clkdiv:5|lpm_add_sub:201|addcore:adder|:183
- 8 - A 05 AND2 0 4 0 3 |clkdiv:5|lpm_add_sub:201|addcore:adder|:187
- 5 - A 11 AND2 0 3 0 4 |clkdiv:5|lpm_add_sub:201|addcore:adder|:195
- 2 - A 08 AND2 0 3 0 1 |clkdiv:5|lpm_add_sub:201|addcore:adder|:203
- 4 - A 10 AND2 0 4 0 2 |clkdiv:5|lpm_add_sub:201|addcore:adder|:207
- 5 - A 10 OR2 0 4 0 23 |clkdiv:5|:12
- 1 - A 10 OR2 0 4 0 2 |clkdiv:5|:27
- 1 - A 05 OR2 s 0 4 0 1 |clkdiv:5|~34~1
- 2 - A 05 OR2 0 4 0 1 |clkdiv:5|:54
- 1 - A 04 OR2 0 4 0 1 |clkdiv:5|:69
- 4 - A 04 AND2 0 3 0 1 |clkdiv:5|:84
- 3 - A 04 OR2 0 3 0 2 |clkdiv:5|:97
- 8 - A 10 DFFE + 0 3 0 2 |clkdiv:5|clk_count22 (|clkdiv:5|:174)
- 7 - A 10 DFFE + 0 2 0 3 |clkdiv:5|clk_count21 (|clkdiv:5|:175)
- 1 - A 08 DFFE + 0 2 0 3 |clkdiv:5|clk_count20 (|clkdiv:5|:176)
- 2 - A 10 DFFE + 0 3 0 3 |clkdiv:5|clk_count19 (|clkdiv:5|:177)
- 3 - A 10 DFFE + 0 2 0 4 |clkdiv:5|clk_count18 (|clkdiv:5|:178)
- 7 - A 11 DFFE + 0 3 0 2 |clkdiv:5|clk_count17 (|clkdiv:5|:179)
- 6 - A 11 DFFE + 0 2 0 3 |clkdiv:5|clk_count16 (|clkdiv:5|:180)
- 6 - A 05 DFFE + 0 2 0 2 |clkdiv:5|clk_count15 (|clkdiv:5|:181)
- 4 - A 05 DFFE + 0 3 0 3 |clkdiv:5|clk_count14 (|clkdiv:5|:182)
- 3 - A 05 DFFE + 0 2 0 4 |clkdiv:5|clk_count13 (|clkdiv:5|:183)
- 4 - A 11 DFFE + 0 2 0 2 |clkdiv:5|clk_count12 (|clkdiv:5|:184)
- 1 - A 11 DFFE + 0 3 0 3 |clkdiv:5|clk_count11 (|clkdiv:5|:185)
- 3 - A 11 DFFE + 0 2 0 4 |clkdiv:5|clk_count10 (|clkdiv:5|:186)
- 8 - A 04 DFFE + 0 3 0 2 |clkdiv:5|clk_count9 (|clkdiv:5|:187)
- 7 - A 04 DFFE + 0 3 0 3 |clkdiv:5|clk_count8 (|clkdiv:5|:188)
- 1 - A 03 DFFE + 0 2 0 4 |clkdiv:5|clk_count7 (|clkdiv:5|:189)
- 5 - A 04 DFFE + 0 2 0 2 |clkdiv:5|clk_count6 (|clkdiv:5|:190)
- 4 - A 01 DFFE + 0 3 0 2 |clkdiv:5|clk_count5 (|clkdiv:5|:191)
- 2 - A 01 DFFE + 0 2 0 3 |clkdiv:5|clk_count4 (|clkdiv:5|:192)
- 7 - A 01 DFFE + 0 2 0 1 |clkdiv:5|clk_count3 (|clkdiv:5|:193)
- 3 - A 01 DFFE + 0 3 0 1 |clkdiv:5|clk_count2 (|clkdiv:5|:194)
- 6 - A 01 DFFE + 0 2 0 2 |clkdiv:5|clk_count1 (|clkdiv:5|:195)
- 5 - A 01 DFFE + 0 1 0 3 |clkdiv:5|clk_count0 (|clkdiv:5|:196)
- 6 - A 10 DFFE + 0 4 0 10 |clkdiv:5|:200
- 5 - B 22 OR2 ! 0 3 0 6 |clkscan3:16|:36
- 6 - B 22 AND2 0 3 0 6 |clkscan3:16|:66
- 7 - B 22 AND2 0 3 0 6 |clkscan3:16|:91
- 2 - B 22 AND2 0 3 0 5 |clkscan3:16|:141
- 2 - B 19 AND2 0 3 0 6 |clkscan3:16|:166
- 3 - B 22 DFFE 0 3 0 12 |clkscan3:16|state2 (|clkscan3:16|:194)
- 1 - B 19 DFFE 0 4 0 13 |clkscan3:16|state1 (|clkscan3:16|:195)
- 4 - B 22 DFFE 0 3 0 12 |clkscan3:16|state0 (|clkscan3:16|:196)
- 2 - B 15 AND2 0 2 0 1 |clkscan3:16|:206
- 4 - B 19 AND2 0 2 0 1 |clkscan3:16|:207
- 2 - B 20 AND2 0 2 0 1 |clkscan3:16|:208
- 3 - B 01 AND2 0 2 0 1 |clkscan3:16|:209
- 3 - B 15 AND2 0 4 0 1 |clkscan3:16|:218
- 5 - B 19 AND2 0 4 0 1 |clkscan3:16|:219
- 2 - B 14 AND2 0 4 0 1 |clkscan3:16|:220
- 4 - B 14 AND2 0 4 0 1 |clkscan3:16|:221
- 1 - B 22 OR2 ! 0 4 0 9 |clkscan3:16|:234
- 4 - B 15 OR2 s 0 4 0 1 |clkscan3:16|~240~1
- 5 - B 15 OR2 s 0 3 0 1 |clkscan3:16|~240~2
- 6 - B 15 OR2 s 0 4 0 1 |clkscan3:16|~240~3
- 6 - B 19 OR2 s 0 4 0 1 |clkscan3:16|~241~1
- 7 - B 19 OR2 s 0 3 0 1 |clkscan3:16|~241~2
- 8 - B 19 OR2 s 0 4 0 1 |clkscan3:16|~241~3
- 3 - B 20 OR2 s 0 4 0 1 |clkscan3:16|~242~1
- 4 - B 20 OR2 s 0 3 0 1 |clkscan3:16|~242~2
- 5 - B 20 OR2 s 0 4 0 1 |clkscan3:16|~242~3
- 4 - B 01 OR2 s 0 4 0 1 |clkscan3:16|~243~1
- 5 - B 01 OR2 s 0 3 0 1 |clkscan3:16|~243~2
- 7 - B 01 OR2 s 0 4 0 1 |clkscan3:16|~243~3
- 1 - B 15 DFFE 0 5 0 16 |clkscan3:16|:244
- 3 - B 19 DFFE 0 5 0 15 |clkscan3:16|:245
- 1 - B 20 DFFE 0 5 0 15 |clkscan3:16|:246
- 2 - B 01 DFFE 0 5 0 16 |clkscan3:16|:247
- 6 - B 01 DFFE 0 3 1 0 |clkscan3:16|:292
- 1 - B 01 DFFE 0 3 1 0 |clkscan3:16|:293
- 8 - B 22 DFFE 0 4 1 0 |clkscan3:16|:294
- 7 - B 24 DFFE 0 3 1 0 |clkscan3:16|:295
- 1 - B 24 DFFE 0 3 1 0 |clkscan3:16|:296
- 3 - B 24 DFFE 0 3 1 0 |clkscan3:16|:297
- 3 - B 11 AND2 0 4 0 1 |p7segment:8|:36
- 1 - B 02 AND2 0 4 0 2 |p7segment:8|:60
- 3 - B 02 AND2 0 4 0 3 |p7segment:8|:144
- 5 - B 03 AND2 s 0 2 0 1 |p7segment:8|~156~1
- 8 - B 02 OR2 s 0 4 0 1 |p7segment:8|~218~1
- 2 - B 02 OR2 s 0 4 0 3 |p7segment:8|~218~2
- 6 - B 07 AND2 ! 0 4 0 7 |p7segment:8|:218
- 3 - B 03 OR2 s 0 4 0 1 |p7segment:8|~227~1
- 4 - B 03 OR2 s 0 4 0 2 |p7segment:8|~227~2
- 1 - B 11 OR2 s 0 3 0 1 |p7segment:8|~227~3
- 1 - B 07 OR2 0 3 1 0 |p7segment:8|:227
- 7 - B 02 OR2 s ! 0 4 0 2 |p7segment:8|~230~1
- 2 - B 11 AND2 s 0 3 0 1 |p7segment:8|~230~2
- 3 - B 07 OR2 0 2 1 0 |p7segment:8|:230
- 8 - B 07 OR2 s 0 3 0 2 |p7segment:8|~233~1
- 2 - B 03 OR2 s 0 4 0 1 |p7segment:8|~233~2
- 5 - B 07 OR2 0 3 1 0 |p7segment:8|:233
- 6 - B 03 OR2 s 0 4 0 1 |p7segment:8|~236~1
- 7 - B 03 OR2 s 0 3 0 1 |p7segment:8|~236~2
- 4 - B 02 OR2 s 0 4 0 1 |p7segment:8|~236~3
- 6 - B 02 OR2 0 2 1 0 |p7segment:8|:236
- 8 - B 03 OR2 s 0 4 0 1 |p7segment:8|~239~1
- 1 - B 03 OR2 0 3 1 0 |p7segment:8|:239
- 2 - B 07 OR2 0 3 1 0 |p7segment:8|:242
- 5 - B 02 OR2 s 0 4 0 1 |p7segment:8|~245~1
- 7 - B 07 OR2 s 0 4 0 1 |p7segment:8|~245~2
- 4 - B 07 OR2 0 2 1 0 |p7segment:8|:245
- 1 - B 16 SOFT s ! 1 0 0 1 reset~1
- 3 - B 23 AND2 0 2 0 1 |timer:15|lpm_add_sub:299|addcore:adder|:55
- 6 - B 13 AND2 0 3 0 1 |timer:15|lpm_add_sub:299|addcore:adder|:59
- 2 - B 17 AND2 0 2 0 1 |timer:15|lpm_add_sub:300|addcore:adder|:55
- 7 - B 17 AND2 0 3 0 1 |timer:15|lpm_add_sub:300|addcore:adder|:59
- 4 - B 18 AND2 0 2 0 1 |timer:15|lpm_add_sub:301|addcore:adder|:55
- 7 - B 18 AND2 0 3 0 1 |timer:15|lpm_add_sub:301|addcore:adder|:59
- 4 - B 08 AND2 0 2 0 1 |timer:15|lpm_add_sub:303|addcore:adder|:55
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