fn_divide.tdf

verilog编写的计算百分比模块

%
    ******************************************************************************
	*   This function is given as a free design, and may be freely distributed   *
	*   and modified, as long as this message remains intact.                    *
	*                                                                            *
	*   Written by Steven Groom ([e-mail])                       *
	*   Revision 1.0                                                             *
    ******************************************************************************
%
include "lpm_compare";
include "lpm_add_sub";
include "lpm_counter";
parameters
(
	lpm_width=8
);
constant endcount=lpm_width-1;
constant bitwidth=ceil(log2(lpm_width));
subdesign fn_divide
(
	clock						:	input;
	go_calc						:	input;	-- signal a start
	divsr[lpm_width-1..0]		:	input;	-- divisor
	divnd[lpm_width-1..0]		:	input;	-- dividend
	quot[lpm_width-1..0]		:	output;	-- quotient
	rem[lpm_width-1..0]			:	output;	-- remainder
	no_calc						:	output;	-- signal finished
)
variable
	process						:	machine with states (idle,calc_1,calc_2,calc_3,calc_4);

	fn_endcount					:	lpm_compare with (lpm_width=bitwidth,
										one_input_is_constant="YES");
	fn_count					:	lpm_counter with (lpm_width=bitwidth);
	fn_sub						:	lpm_add_sub with (lpm_width=lpm_width,
										lpm_representation="UNSIGNED",
										lpm_direction="SUB");

	dvnd[lpm_width-1..0]		:	dffe;
	quot[lpm_width-1..0]		:	dffe;
	flag						:	dffe;
begin
	process.clk=global(clock);
	dvnd[].clk=clock;
	quot[].clk=clock;
	fn_count.clock=clock;
	flag.clk=clock;
	fn_endcount.dataa[]=fn_count.q[];
	fn_endcount.datab[]=endcount;
	fn_sub.dataa[]=quot[];
	fn_sub.datab[]=divsr[];
	rem[]=dvnd[];
	case process is
		when idle =>
			fn_count.sclr=vcc;
			dvnd[]=divnd[];
			flag.ena=vcc;
			if go_calc then
				dvnd[].ena=vcc;
				quot[].ena=vcc;
				process=calc_1;
			end if;
		when calc_1 =>
			dvnd[lpm_width-1..1]=dvnd[lpm_width-2..0];
			dvnd[0]=flag;
			flag=dvnd[lpm_width-1];
			flag.ena=vcc;
			dvnd[].ena=vcc;
			process=calc_2;
		when calc_2 =>
			quot[lpm_width-1..1]=quot[lpm_width-2..0];
			quot[0]=flag;
			flag=quot[lpm_width-1];
			flag.ena=vcc;
			quot[].ena=vcc;
			process=calc_3;
		when calc_3 =>
			if fn_endcount.aeb then
				quot[]=(dvnd[lpm_width-2..0],fn_sub.cout);
				quot[].ena=vcc;
				if fn_sub.cout then
					dvnd[]=fn_sub.result[];
				else
					dvnd[]=quot[];
				end if;
				dvnd[].ena=vcc;
				process=calc_4;
			else
				quot[]=fn_sub.result[];
				quot[].ena=fn_sub.cout;
				flag.ena=vcc;
				flag=fn_sub.cout;
				fn_count.cnt_en=vcc;
				process=calc_1;
			end if;
		when calc_4 =>
			no_calc=vcc;
			process=idle;
	end case;
end;