fn_multiply.tdf

verilog编写的计算百分比模块

%
    ******************************************************************************
	*   This function is given as a free design, and may be freely distributed   *
	*   and modified, as long as this message remains intact.                    *
	*                                                                            *
	*   Written by Steven Groom ([e-mail])                       *
	*   Revision 1.0                                                             *
    ******************************************************************************
%
include "lpm_add_sub";
include "lpm_compare";
parameters
(
	lpm_width=16
);
subdesign fn_multiply
(
	clock						:	input;
	go_calc						:	input;	-- signal start
	dataa[lpm_width-1..0]		:	input;	-- data inputs
	datab[lpm_width-1..0]		:	input;	-- data inputs
	result[lpm_width*2-1..0]	:	output;	-- the full result
	no_calc						:	output;	-- signal finished
)
variable
	process						:	machine with states (idle,calc1);

	fn_add						:	lpm_add_sub with (lpm_width=lpm_width*2,
										lpm_direction="ADD",lpm_representation="UNSIGNED");
	fn_complete					:	lpm_compare with (lpm_width=lpm_width,
										one_input_is_constant="YES");

	rega[lpm_width-1..0]		:	dffe;
	regb[lpm_width*2-1..0]		:	dffe;
	result[lpm_width*2-1..0]	:	dffe;
begin
	rega[].clk=global(clock);
	regb[].clk=clock;
	result[].clk=clock;
	process.clk=clock;
	fn_add.dataa[]=regb[];
	fn_add.datab[]=result[];
	fn_complete.dataa[lpm_width-1..0]=rega[];
	fn_complete.datab[]=0;
	case process is
		when idle =>
			rega[]=dataa[];
			regb[]=(0,datab[]);
			result[]=gnd;
			if go_calc then
				rega[].ena=vcc;
				regb[].ena=vcc;
				result[].ena=vcc;
				process=calc1;
			end if;
		when calc1 =>
			result[]=fn_add.result[];
			result[].ena=rega[0];
			rega[lpm_width-2..0]=rega[lpm_width-1..1];
			rega[].ena=vcc;
			regb[lpm_width*2-1..1]=regb[lpm_width*2-2..0];
			regb[].ena=vcc;
			if fn_complete.aeb then
				no_calc=vcc;
				process=idle;
			end if;
	end case;
end;