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V 的代码
timescale.v
`timescale 1ns /100ps
timescale.v
`timescale 1ns /100ps
clock.v
//
// The clock for internal clock and sdram clock with two PLL
//
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "define.v"
module clock(clk0,pll0,s
aaa.v
// megafunction wizard: %ALTPLL%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altpll
// ============================================================
// File Name: aaa.v
// Megafunctio
ram.v
// megafunction wizard: %RAM: 2-PORT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: altsyncram
// ============================================================
// File Name: ram.v
// Me
top.v
// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "define.v"
module top(
clk0,rstn,
led,
`ifdef SPI
sck_o,
mosi_o,
miso_i,
csn_o
`endi
pic.v
//
// SYNTHETIC PIC 2.0 4/23/98
//
// This is a synthesizable Microchip 16C57 compatible
// microcontroller. This core is not intended as a high fi
shifter.v
module shifter(in,clock,reset,out);
input in,clock,reset;
output [7:0] out;
reg [7:0] out;
always@(posedge clock)
begin
if(reset)
out=8'b0000;
else
test.v
//////////////////////////////////////////////////////////////
////////Module name :test /////////////
////////Function :used to test
all.v
module all (a,b,y);
input [7:0] a,b;
output [8:0] y;
function [8:0] add_It_10;
input [7:0] a,b;
reg [7:0] temp;
begin
if(b