top.v

FPGA直接读取SD卡扇区数据

// synopsys translate_off
`include "timescale.v"
// synopsys translate_on
`include "define.v"
module top(
    clk0,rstn,
    led,
`ifdef SPI
    sck_o,  
    mosi_o, 
    miso_i, 
    csn_o
`endif
); 
output led;

	input clk0;
	input rstn;
`ifdef SPI
    output      sck_o;  
    output      mosi_o; 
    input       miso_i; 
    output 	    csn_o; 
`endif

	wire clk_i;
	wire clk_i0;
	wire vga_clk;
	
	aaa clk_module(
	.inclk0(clk0),
	.c0(clk_i   ),
	.c1(sdram_clk)
	);

reg			rst_r;
reg			rst_i;

always @(posedge clk_i or negedge rstn)
	if (~rstn)
		rst_r <= 1'b1;
	else
		rst_r <= #1 1'b0;

always @(posedge clk_i)
	rst_i <= #1 rst_r;	   
		

`ifdef SPI
//
// spiMaster core slave i/f wires
//
wire	[31:0]		wb_sds_dat_i;
wire 	[7:0]   	wb_sds_dat_8bit;
wire	[31:0]		wb_sds_dat_o;
wire	[31:0]		wb_sds_adr_i;
wire 	[3:0]      	wb_sds_sel_i;
wire			wb_sds_we_i;
wire			wb_sds_cyc_i;
wire			wb_sds_stb_i;
wire			wb_sds_ack_o;
spiMaster u_spiMaster (
 
  .clk_i     (clk_i),
  .rst_i     (rst_i),
  .address_i (wb_sds_adr_i[7:0]),
  .data_i    (wb_sds_dat_i[7:0]),
  .data_o    (wb_sds_dat_8bit),
  .strobe_i  (wb_sds_stb_i),
  .we_i      (wb_sds_we_i),
  .ack_o     (wb_sds_ack_o),

 
  .spiSysClk  (clk0),
  .spiClkOut  (sck_o    ),
  .spiDataIn  (miso_i   ),
  .spiDataOut (mosi_o   ),
  .spiCS_n    (csn_o    )
);

assign wb_sds_dat_o = {wb_sds_dat_8bit, wb_sds_dat_8bit, wb_sds_dat_8bit, wb_sds_dat_8bit};
`endif 




wire[31:0]	wb_eth_adr_o;
wire[31:0] 	wb_eth_dat_o;
wire[31:0] 	wb_eth_dat_i;
wire[3 : 0]	wb_eth_sel_o;
wire    	wb_eth_we_o;
wire	    wb_eth_stb_o;
wire  		wb_eth_cyc_o;
wire    	wb_eth_ack_i;
wire        eth_int_o;	

ctrl_eth  ctrl_eth(
	
	
	.wb_clk_i  ( clk_i         ),
	.wb_rst_i  ( rst_i         ),
	.wb_adr_o  ( wb_eth_adr_o  ),
	.wb_dat_i  ( wb_eth_dat_i  ),
	.wb_dat_o  ( wb_eth_dat_o  ),
	.wb_sel_o  ( wb_eth_sel_o  ),
	.wb_we_o   ( wb_eth_we_o   ), 
	.wb_stb_o  ( wb_eth_stb_o  ),
	.wb_cyc_o  ( wb_eth_cyc_o  ),
	.wb_ack_i  ( wb_eth_ack_i  ),
	.led(led)
);


tc_top
#(  
`APP_ADDR_DEC_W,
`APP_ADDR_SD) 
tc_top
(

	.wb_clk_i	( clk_i ),
	.wb_rst_i	( rst_i ),


	.i0_wb_cyc_i	( wb_eth_cyc_o ),
	.i0_wb_stb_i	( wb_eth_stb_o ),
	.i0_wb_cab_i	( 1'b0 ),
	.i0_wb_adr_i	( wb_eth_adr_o ),
	.i0_wb_sel_i	( wb_eth_sel_o ),
	.i0_wb_we_i		( wb_eth_we_o  ),
	.i0_wb_dat_i	( wb_eth_dat_o ),
	.i0_wb_dat_o	( wb_eth_dat_i ),
	.i0_wb_ack_o	( wb_eth_ack_i ),
	.i0_wb_err_o	(      ), 

	.i1_wb_cyc_i	( 1'b0 ),
	.i1_wb_stb_i	( 1'b0 ),
	.i1_wb_cab_i	( 1'b0 ),
	.i1_wb_adr_i	( 32'h0000_0000 ),
	.i1_wb_sel_i	( 4'b0000 ),
	.i1_wb_we_i		( 1'b0 ),
	.i1_wb_dat_i	( 32'h0000_0000 ),
	.i1_wb_dat_o	( ),
	.i1_wb_ack_o	( ),
	.i1_wb_err_o	( ),


	.i2_wb_cyc_i	( 1'b0 ),
	.i2_wb_stb_i	( 1'b0 ),
	.i2_wb_cab_i	( 1'b0 ),
	.i2_wb_adr_i	( 32'h0000_0000 ),
	.i2_wb_sel_i	( 4'b0000 ),
	.i2_wb_we_i		( 1'b0 ),
	.i2_wb_dat_i	( 32'h0000_0000 ),
	.i2_wb_dat_o	( ),
	.i2_wb_ack_o	( ),
	.i2_wb_err_o	( ),


	.i3_wb_cyc_i	( 1'b0 ),
	.i3_wb_stb_i	( 1'b0 ),
	.i3_wb_cab_i	( 1'b0 ),
	.i3_wb_adr_i	( 32'h0000_0000 ),
	.i3_wb_sel_i	( 4'b0000 ),
	.i3_wb_we_i		( 1'b0 ),
	.i3_wb_dat_i	( 32'h0000_0000 ),
	.i3_wb_dat_o	( ),
	.i3_wb_ack_o	( ),
	.i3_wb_err_o	( ),


	.i4_wb_cyc_i	( 1'b0 ),
	.i4_wb_stb_i	( 1'b0 ),
	.i4_wb_cab_i	( 1'b0 ),
	.i4_wb_adr_i	( 32'h0000_0000 ),
	.i4_wb_sel_i	( 4'b0000 ),
	.i4_wb_we_i		( 1'b0 ),
	.i4_wb_dat_i	( 32'h0000_0000 ),
	.i4_wb_dat_o	( ),
	.i4_wb_ack_o	( ),
	.i4_wb_err_o	( ),


	.i5_wb_cyc_i	( 1'b0 ),
	.i5_wb_stb_i	( 1'b0 ),
	.i5_wb_cab_i	( 1'b0 ),
	.i5_wb_adr_i	( 32'h0000_0000 ),
	.i5_wb_sel_i	( 4'b0000 ),
	.i5_wb_we_i		( 1'b0 ),
	.i5_wb_dat_i	( 32'h0000_0000 ),
	.i5_wb_dat_o	( ),
	.i5_wb_ack_o	( ),
	.i5_wb_err_o	( ),

	.i6_wb_cyc_i	( 1'b0 ),
	.i6_wb_stb_i	( 1'b0 ),
	.i6_wb_cab_i	( 1'b0 ),
	.i6_wb_adr_i	( 32'h0000_0000 ),
	.i6_wb_sel_i	( 4'b0000 ),
	.i6_wb_we_i		( 1'b0 ),
	.i6_wb_dat_i	( 32'h0000_0000 ),
	.i6_wb_dat_o	( ),
	.i6_wb_ack_o	( ),
	.i6_wb_err_o	( ),

	.i7_wb_cyc_i	( 1'b0 ),
	.i7_wb_stb_i	( 1'b0 ),
	.i7_wb_cab_i	( 1'b0 ),
	.i7_wb_adr_i	( 32'h0000_0000 ),
	.i7_wb_sel_i	( 4'b0000 ),
	.i7_wb_we_i		( 1'b0 ),
	.i7_wb_dat_i	( 32'h0000_0000 ),
	.i7_wb_dat_o	( ),
	.i7_wb_ack_o	( ),
	.i7_wb_err_o	( ),

  	.t0_wb_cyc_o	( wb_sds_cyc_i ),
	.t0_wb_stb_o	( wb_sds_stb_i ),
	.t0_wb_cab_o	( wb_sds_cab_i),
	.t0_wb_adr_o	( wb_sds_adr_i),
	.t0_wb_sel_o	( wb_sds_sel_i ),
	.t0_wb_we_o	    ( wb_sds_we_i),
	.t0_wb_dat_o	( wb_sds_dat_i),
	.t0_wb_dat_i	( wb_sds_dat_o ),
	.t0_wb_ack_i	( wb_sds_ack_o ),
	.t0_wb_err_i	( 1'b0 ),

    .t1_wb_cyc_o	(  ),
	.t1_wb_stb_o	(  ),
	.t1_wb_cab_o	(  ),
	.t1_wb_adr_o	(  ),
	.t1_wb_sel_o	(  ),
	.t1_wb_we_o	    (  ),
	.t1_wb_dat_o	(  ),
	.t1_wb_dat_i	( 32'h0000_0000 ),
	.t1_wb_ack_i	( 1'b0 ),
	.t1_wb_err_i	( 1'b0 ),

	.t2_wb_cyc_o	(  ),
	.t2_wb_stb_o	(  ),
	.t2_wb_cab_o	(  ),
	.t2_wb_adr_o	(  ),
	.t2_wb_sel_o	(  ),
	.t2_wb_we_o	    (  ),
	.t2_wb_dat_o	(  ),
	.t2_wb_dat_i	( 32'h0000_0000 ),
	.t2_wb_ack_i	( 1'b0 ),
	.t2_wb_err_i	( 1'b0 ),

	.t3_wb_cyc_o	(  ),
	.t3_wb_stb_o	(  ),
	.t3_wb_cab_o	(  ),
	.t3_wb_adr_o	(  ),
	.t3_wb_sel_o	(  ),
	.t3_wb_we_o	    (  ),
	.t3_wb_dat_o	(  ),
	.t3_wb_dat_i	( 32'h0000_0000 ),
	.t3_wb_ack_i	( 1'b0 ),
	.t3_wb_err_i	( 1'b0 ),

	.t4_wb_cyc_o	(  ),
	.t4_wb_stb_o	(  ),
	.t4_wb_cab_o	(  ),
	.t4_wb_adr_o	(  ),
	.t4_wb_sel_o	(  ),
	.t4_wb_we_o	    (  ),
	.t4_wb_dat_o	(  ),
	.t4_wb_dat_i	( 32'h0000_0000 ),
	.t4_wb_ack_i	( 1'b0 ),
	.t4_wb_err_i	( 1'b0 ),

	.t5_wb_cyc_o	(  ),
	.t5_wb_stb_o	(  ),
	.t5_wb_cab_o	(  ),
	.t5_wb_adr_o	(  ),
	.t5_wb_sel_o	(  ),
	.t5_wb_we_o	    (  ),
	.t5_wb_dat_o	(  ),
	.t5_wb_dat_i	( 32'h0000_0000 ),
	.t5_wb_ack_i	( 1'b0 ),
	.t5_wb_err_i	( 1'b0 ),

	.t6_wb_cyc_o	(  ),
	.t6_wb_stb_o	(  ),
	.t6_wb_cab_o	(  ),
	.t6_wb_adr_o	(  ),
	.t6_wb_sel_o	(  ),
	.t6_wb_we_o		(  ),
	.t6_wb_dat_o	(  ),
	.t6_wb_dat_i	( 32'h0000_0000 ),
	.t6_wb_ack_i	( 1'b0 ),
	.t6_wb_err_i	( 1'b0 ),  	

	.t7_wb_cyc_o	(  ),
	.t7_wb_stb_o	(  ),
	.t7_wb_cab_o	(  ),
	.t7_wb_adr_o	(  ),
	.t7_wb_sel_o	(  ),
	.t7_wb_we_o		(  ),
	.t7_wb_dat_o	(  ),
	.t7_wb_dat_i	( 32'h0000_0000 ),
	.t7_wb_ack_i	( 1'b0 ),
	.t7_wb_err_i	( 1'b0 ) 
);

endmodule