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V 的代码
onehot.v
//
// Just a little demo of some FSM techniques, including One-Hot and
// using 'default' settings and the case statements to selectively
// update registers (sort of like J-K flip-flops).
//
//
dds.v
//
//
// This is just a little demo of DDS. It doesn't have any cool features
// or anything..
//
module dds (
clk,
reset,
din,
dout
);
parameter W = 12;
input
framer.v
//
// Simple example of a "framer". In this case, an MPEG framer where
// data is sent in 188-byte frames which begin with a special SYNC character
// defined as 47 hex. Framing must, of course,
fifo.v
// Synchronous FIFO. 4 x 16 bit words.
//
module fifo (clk, rstp, din, writep, readp, dout, emptyp, fullp);
input clk;
input rstp;
input [15:0] din;
input readp;
input writep;
output [15:
compare.v
module compare(a,b,equal);
parameter size=1;
input [size-1:0]a,b;
output equal;
assign equal=(a==b)?1:0;
endmodule
binarytogray.v
module binarytogray (clk, reset, binary_input, gray_output);
input clk, reset;
input [3:0] binary_input;
output gray_output;
reg [3:0] gray_output;
always @ (posedge cl
nco.v
//
// NCO Demo (Numerically controlled Oscillator).
//
// One type of NCO is based on the idea of a continuously wrapping modulo
// counter. The NCO is a programmable modulo counter. For example
string.v
//
// Demonstrate how to display strings for a particular signal.
// This allows you to see a text string for a bus, which at times, might
// help out in debugging. This is not intended for synthe
clock.v
/*
本实验实现一个能显示小时，分钟，秒的数字时钟。
*/
module clock(clk,rst,dataout,en);
input clk,rst;
output[7:0] dataout;
reg[7:0] dataout;
output[7:0] en;
reg[7:0] en;
reg[3:0] dataout_buf[7:0];
reg[25:0] cn
cmp.v
/*
两个4位二进制数的大小比较，结果输出到数码管显示
*/
module cmp(a,b,c,en);
input[3:0] a,b;
output[7:0] c;
reg[7:0] c;
output[7:0] en;
wire[3:0] c_tmp;
assign en=0;
assign c_tmp=(a>=b)? 1:0;
always@(c_t