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system.v
//////////////////////////////////////////////////////////////////////////
// system //
//author:ShengYu Shen from National University of Defence Technology //
//create time: 2001 3 19
memorycontroller.v
//////////////////////////////////////////////////////////////////////////
// memory controller //
// //
//author:ShengYu Shen from national unversity of defense echnology //
//create
cachememory.v
`include "Def_StructureParameter.v"
module CacheMemory( in_CacheMemoryAccessEnable,
in_CacheMemoryAccessRW,
in_CacheMemoryAccessBW,
in_CacheMemoryAccessAddress,
in_CacheMemoryWriteV
datacachecontroller.v
`include "Def_StructureParameter.v"
`include "Def_DataCacheController.v"
module DataCacheController( //signal between mem and DataCacheController
in_DataCacheAddress, //data address
io_
datacachememory.v
`include "Def_StructureParameter.v"
module DataCacheMemory( in_CacheMemoryAccessEnable,
in_CacheMemoryAccessRW,
in_CacheMemoryAccessBW,
in_CacheMemoryAccessAddress,
in_CacheMemoryWr
mul.v
//the lowest bit is the rest bit
//the other bits is the decoded part result
function [34:0] decode;
input [2:0] threebit;
input [33:0] amanadj;
begin
case(threebit)
3'b000,3'b111: begin
registerfile.v
`include "Def_RegisterFile.v"
`include "Def_Mode.v"
//this register file support 4 reads and 3 write
module RegisterFile( //change of state
in_IfChangeState, //this port means access other ba
interruptpriority.v
module InterruptPriority(//interrupt signal
Fiq,
Irq,
//interrupt mask
FiqDisable,
IrqDisable,
//output interrupt signal
TrueFiq,
TrueIrq
);
input Fiq,Irq,Fiq
multp.v
// megafunction wizard: %LPM_MULT%
// GENERATION: STANDARD
// VERSION: WM1.0
// MODULE: lpm_mult
// ============================================================
// File Name: MULTP.v
// Megaf
cmultiplex.v
`timescale 1 ps / 1 ps
module CMULTIPLEX (ia, qa, ib, qb, iout, qout, clk, clkena, reset,tempout);
parameter word_in_size = 16;
input [word_in_size-1:0] ia, ib, qa, qb;
output [word_in_size-1:0] iout