cmultiplex.v

复乘法器的FPGA实现

`timescale 1 ps / 1 ps
module CMULTIPLEX (ia, qa, ib, qb, iout, qout, clk, clkena, reset,tempout);
parameter word_in_size = 16;

input [word_in_size-1:0] ia, ib, qa, qb;
output [word_in_size-1:0] iout, qout;
reg [word_in_size-1:0] iout, qout;
input clk, clkena, reset;
output [31:0] tempout;

reg [word_in_size-1:0] sigbuf1, sigbuf2, sigbuf3, sigbuf4;
reg [word_in_size-1:0] sigbuf5, sigbuf6, sigbuf7, sigbuf8;
wire [word_in_size-1:0] sum1, sum2, sum3, diff1, diff2, tmp1, tmp2, tmp3, tmp4;
wire [2*word_in_size-1:0] product1, product2,product3;

assign tmp1 = sigbuf2;
assign tmp2 = sigbuf4;
assign tmp3 = sigbuf6;
assign tmp4 = sigbuf8;

always @ (posedge clk or posedge reset)
begin
	if(reset)
	begin
		sigbuf1 <= 0;
		sigbuf2 <= 0;
		sigbuf3 <= 0;
		sigbuf4 <= 0;
		sigbuf5 <= 0;
		sigbuf6 <= 0;
		sigbuf7 <= 0;
		sigbuf8 <= 0;
		iout <= 0;
		qout <= 0;
	end
	else
	begin
	   if(clkena)
	   begin
   		   sigbuf2 <= sigbuf1;
		   sigbuf1 <= sum1;
		   sigbuf4 <= sigbuf3;
		   sigbuf3 <= sum2;
		   sigbuf6 <= sigbuf5;
		   sigbuf5 <= sum3;
		   sigbuf8 <= sigbuf7;
		   sigbuf7 <= diff1;
		   iout <= tmp4;
		   qout <= diff2;
		end
	end
end
assign tempout =  sum1;
ADDSUB_16_0 add1(
	.add_sub(1'b1),
	.dataa(ia),
	.datab(qa),
	.result(sum1));
// ia + qa = 300
	
ADDSUB_16_0 add2(
	.add_sub(1'b1),
	.dataa(ib),
	.datab(qb),
	.result(sum2));

//ib + qb = 700
	
ADDSUB_16_0 add3(
	.add_sub(1'b1),
	.dataa(product1[2*word_in_size-2:word_in_size-1]),
	.datab(product2[2*word_in_size-2:word_in_size-1]),
	.result(sum3));
//sum3 = product1+ product2 = 16

ADDSUB_16_0 sub1(
	.add_sub(1'b0),
	.dataa(product1[2*word_in_size-2:word_in_size-1]),
	.datab(product2[2*word_in_size-2:word_in_size-1]),
	.result(diff1));

//diff1 = product1 - product2 = a
	
ADDSUB_16_0 sub2(
	.add_sub(1'b0),
	.dataa(product3[2*word_in_size-2:word_in_size-1]),
	.datab(tmp3),
	.result(diff2));
//diff2 = product- sum3 =14

MULTP mult1(
	.aclr(reset),
	.clken(clkena),
	.clock(clk),
	.dataa(ia),
	.datab(ib),
	.result(product1));
//ia * ib = 200 * 400 = 80000


MULTP mult2(
	.aclr(reset),
	.clken(clkena),
	.clock(clk),
	.dataa(qa),
	.datab(qb),
	.result(product2));
	
	
// qa * qa = 100 * 300 = 30000;

MULTP mult3(
	.aclr(reset),
	.clken(clkena),
	.clock(clk),
	.dataa(tmp1),
	.datab(tmp2),
	.result(product3));
// sum1 * sum 2 = 300 * 700 =	150000
	
endmodule