_primary.vhd

来自「复乘法器的FPGA实现」· VHDL 代码 · 共 20 行

library verilog;
use verilog.vl_types.all;
entity CMULTIPLEX is
    generic(
        word_in_size    : integer := 16
    );
    port(
        clk             : in     vl_logic;
        clkena          : in     vl_logic;
        reset           : in     vl_logic;
        ia              : in     vl_logic_vector;
        qa              : in     vl_logic_vector;
        ib              : in     vl_logic_vector;
        qb              : in     vl_logic_vector;
        iout            : out    vl_logic_vector;
        qout            : out    vl_logic_vector;
        tempout         : out    vl_logic_vector(31 downto 0)
    );
end CMULTIPLEX;