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psr.v
`include "Def_psr.v"
`include "Def_Mode.v"
module StatusRegisters( //change of state
in_IfChangeState, //this port means only SWI or FIQ or IRQ or UND or ABT
in_ChangeStateAction,
//wr
memorymux.v
module MemoryMux(//instruction cache signal
out_InstructionBus,
out_InstructionWait,
in_InstructionAddress,
in_InstructionRequest,
//data cache signal
io_DataBus,
ou
testinstruction.v
//add r0 with 11111111 to r1
`define TestInstruction_Add1 32'b1110_0010_1000_0000_0001_0000_1111_1111
//add r1 with 00000000 to r3
`define TestInstruction_Add2 32'b1110_0010_1000_0001_0011_0000_000
nnarm.v
`include "Def_StructureParameter.v"
`include "InstructionPreFetch.v"
`include "MemoryController.v"
`include "InstructionCacheController.v"
`include "DataCacheController.v"
`include "IF.v"
`inclu
bustransfer.v
module BusTransfer(in_WriteBus,
out_LeftReadBus,
out_RightReadBus,
out_ThirdReadBus,
//above is the Buses
//below is control signal
in_WriteToLeftRead,
in_WriteToRightRead,
tb_if.v
`include "Def_StructureParameter.v"
`include "InstructionPreFetch.v"
`include "MemoryController.v"
`include "InstructionCacheController.v"
`include "Pipeline.v"
module tb_InstructionPreFetch;
arbitrator.v
module Arbitrator(in_ALUWriteRequest,
out_ALUWriteEnable);
input in_ALUWriteRequest;
output out_ALUWriteEnable;
reg out_ALUWriteEnable;
always @(in_ALUWriteRequest)
begin
if(in_ALUWriteReq
instructionprefetch.v
//////////////////////////////////////////////////////////////////
// the instruction prefetch buffer //
//Note:the orgnization of the Instruction PreFetche buffer //
//serious depend on the ASI
cam.v
//when in_CAMWriteEnable==1'b0,CAM will behave as a comparator
//if one of its entry match to the in_CAMInput,it will make out_CAMMatchUp=1'b1 and out_CAMMatchResult=entry number
//when in_CAMWrite
instructioncachecontroller.v
//////////////////////////////////////////////////////////////////////////
// instruction cache controller //
// //
//author:ShengYu Shen from National University of Defense Technology