嵌入式CAN模块 联系 杨迪 15336417867 0531-55508458 QQ：1347978253 htp://www.easyele.cn CAN (Controller Area Network)即控制器局域网络,属于工业现场总线的范畴。与一般的通信总线相比,CAN总线的数据通信具有突出的可靠性 、实时性和灵活性。嵌入式CAN模块控制器功能强，通信效率高,是公认的稳定可靠的通讯模式，广泛应用于消防安防、智能楼宇、酒店门锁、 煤矿通讯、船舶运输等应用领域。本系统采汽车级CPU，更保障其稳定性。客户可以放心使用。 嵌入式CAN模块 转 RS232 RS485 ttl ，可以帮助用户快速实现具有CAN-bus通讯接口的仪器、仪表设备的项目设计，模块集成了8bit微处理器 CAN控制器、CAN收发器、总线保护于一身，所有元器件布置在一个微型的封装模块之内，用户只需要知道RS232的通讯即可实现CAN通讯。客户 可以方便使用。 在使用过程中，嵌入式CAN模块可以工作于二种模式：透明传输模式和透明数据模式。并且提供上位机设计，UART输出时可以为ttl电平，RS232 或RS485，对应订货型号为 CAN-module-ttl / rs232 / 485。客户应注意。 嵌入式CAN模块可以在CAN与RS232间精确的转换信息，让您更方便的通过PC或带RS232端口的设备与CAN设备通讯。欢迎大家咨询选购嵌入式CAN 模块，是我公司自主研发生产，完全拥有知识产权，专业的产品包装，详细的资料光盘，性价比高，专业公司操作，及时的技术支持，完善的 售后服务，解决客户的后顾之忧。
上传时间： 2013-11-27
上传用户：13925096126
The PCA9549 provides eight bits of high speed ttl-compatible bus switching controlledby the I2C-bus. The low ON-state resistance of the switch allows connections to be madewith minimal propagation delay. Any individual A to B channel or combination of channelscan be selected via the I2C-bus, determined by the contents of the programmable Controlregister. When the I2C-bus bit is HIGH (logic 1), the switch is on and data can flow fromPort A to Port B, or vice versa. When the I2C-bus bit is LOW (logic 0), the switch is open,creating a high-impedance state between the two ports, which stops the data flow.An active LOW reset input (RESET) allows the PCA9549 to recover from a situationwhere the I2C-bus is stuck in a LOW state. Pulling the RESET pin LOW resets the I2C-busstate machine and causes all the bits to be open, as does the internal power-on resetfunction.
上传时间： 2014-11-22
上传用户：xcy122677
The TRS232E is a dual driver/receiver that includes a capacitive voltage generator to supply TIA/RS-232-Fvoltage levels from a single 5-V supply. Each receiver converts TIA/RS-232-F inputs to 5-V ttl/CMOS levels.This receiver has a typical threshold of 1.3 V, a typical hysteresis of 0.5 V, and can accept ±30-V inputs. Eachdriver converts ttl/CMOS input levels into TIA/RS-232-F levels. The driver, receiver, and voltage-generatorfunctions are available as cells in the Texas Instruments LinASIC™ library.
上传时间： 2013-10-07
上传用户：waitingfy
82C54是专为Intel系列微处理机而设计的一种可编程时间间隔定时器/计数器，它是一种通用芯片，在系统软件中可以把多级定时元素当成输入/输出端口中的一个阵列看待。1. 与所有Intel系列兼容2. 操作速度高，与8MHz的8086、80186一起可实现“零等待状态”的操作。3. 可处理从直流到10M频率的输入。4. 适应性强5. 三个独立的16位计数器6. 低功耗的CHMOS7. 与ttl完全兼容8. 6 种可编程的计数模式9. 以二进制或BCD计数10. 状态读返回命令
上传时间： 2013-11-15
上传用户：elinuxzj
82C55A是高性能，工业标准，并行I/O的LSI外围芯片；提供24条I/O脚线。 在三种主要的操作方式下分组进行程序设计82C88A的几个特点：(1)与所有Intel系列微处理器兼容；(2)有较高的操作速度；(3)24条可编程I/O脚线；(4)底功耗的CHMOS；(5)与ttl兼容；(6)拥有控制字读回功能；（7）拥有直接置位/复位功能；（8）在所有I/O输出端口有2.5mA DC驱动能力；（9）适应性强。方式0操作称为简单I/O操作，是指端口的信号线可工作在电平敏感输入方式或锁存输出。所以，须将控制寄存器设计为：控制寄存器中:D7=1; D6 D5=00; D2=0。D7位为1代表一个有效的方式。通过对D4 D3 D1和D0的置位/复位来实现端口A及端口B是输入或输出。P56表2-1列出了操作方式0端口管脚功能。
上传时间： 2013-10-25
上传用户：brilliantchen
In this document, the term Ô60xÕ is used to denote a 32-bit microprocessor from the PowerPC architecture family that conforms to the bus interface of the PowerPC 601ª, PowerPC 603ª, or PowerPC 604 microprocessors. Note that this does not include the PowerPC 602ª microprocessor which has a multiplexed address/data bus. 60x processors implement the PowerPC architecture as it is speciÞed for 32-bit addressing, which provides 32-bit effective (logical) addresses, integer data types of 8, 16, and 32 bits,and ßoating-point data types of 32 and 64 bits (single-precision and double-precision).1.1 Overview The MPC106 provides an integrated high-bandwidth, high-performance, ttl-compatible interface between a 60x processor, a secondary (L2) cache or additional (up to four total) 60x processors, the PCI bus,and main memory. This section provides a block diagram showing the major functional units of the 106 and describes brießy how those units interact.Figure 1 shows the major functional units within the 106. Note that this is a conceptual block diagram intended to show the basic features rather than an attempt to show how these features are physically implemented on the device.
上传时间： 2013-10-08
上传用户：18711024007
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between ttl-VIL and ttl-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of thettl-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for ttl components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.For input signals, which do not provide the required rise/fall times, external circuitry mustbe used to shape the signal transitions.In the attached diagram, the effect of the sample rate is shown. The numbers 1 to 5 in thediagram represent possible sample points. Waveform a) shows the result if the inputsignal transition time through the undefined ttl-level area is less than the time distancebetween the sample points (sampling at 1, 2, 3, and 4). Waveform b) can be the result ifthe sampling is performed more than once within the undefined area (sampling at 1, 2, 5,3, and 4).Sample points:1. Evaluation of the signal clearly results in a low level2. Either a low or a high level can be sampled here. If low is sampled, no transition willbe detected. If the sample results in a high level, a transition is detected, and anappropriate action (e.g. capture) might take place.3. Evaluation here clearly results in a high level. If the previous sample 2) had alreadydetected a high, there is no change. If the previous sample 2) showed a low, atransition from low to high is detected now.
上传时间： 2013-10-23
上传用户：copu
All inputs of the C16x family have Schmitt-Trigger input characteristics. These Schmitt-Triggers are intended to always provide proper internal low and high levels, even if anundefined voltage level (between ttl-VIL and ttl-VIH) is externally applied to the pin.The hysteresis of these inputs, however, is very small, and can not be properly used in anapplication to suppress signal noise, and to shape slow rising/falling input transitions.Thus, it must be taken care that rising/falling input signals pass the undefined area of thettl-specification between VIL and VIH with a sufficient rise/fall time, as generally usualand specified for ttl components (e.g. 74LS series: gates 1V/us, clock inputs 20V/us).The effect of the implemented Schmitt-Trigger is that even if the input signal remains inthe undefined area, well defined low/high levels are generated internally. Note that allinput signals are evaluated at specific sample points (depending on the input and theperipheral function connected to it), at that signal transitions are detected if twoconsecutive samples show different levels. Thus, only the current level of an input signalat these sample points is relevant, that means, the necessary rise/fall times of the inputsignal is only dependant on the sample rate, that is the distance in time between twoconsecutive evaluation time points. If an input signal, for instance, is sampled throughsoftware every 10us, it is irrelevant, which input level would be seen between thesamples. Thus, it would be allowable for the signal to take 10us to pass through theundefined area. Due to the sample rate of 10us, it is assured that only one sample canoccur while the signal is within the undefined area, and no incorrect transition will bedetected. For inputs which are connected to a peripheral function, e.g. capture inputs, thesample rate is determined by the clock cycle of the peripheral unit. In the case of theCAPCOM unit this means a sample rate of 400ns @ 20MHz CPU clock. This requiresinput signals to pass through the undefined area within these 400ns in order to avoidmultiple capture events.
上传时间： 2014-04-02
上传用户：han_zh
7.1 并行接口概述并行接口和串行接口的结构示意图并行接口传输速率高，一般不要求固定格式，但不适合长距离数据传输7.2 可编程并行接口芯片82C55 7.2.1 8255的基本功能 8255具有2个独立的8位I/O口（A口和B口）和2个独立的4位I/O（C口上半部和C口下半部），提供ttl兼容的并行接口。作为输入时提供三态缓冲器功能，作为输出时提供数据锁存功能。其中，A口具有双向传输功能。8255有3种工作方式，方式0、方式1和方式2，能使用无条件、查询和中断等多种数据传送方式完成CPU与I/O设备之间的数据交换。B口和C口的引脚具有达林顿复合晶体管驱动能力，在1.5V时输出1mA电流，适于作输出端口。C口除用做数据口外，当8255工作在方式1和方式2时，C口的部分引脚作为固定的联络信号线。
标签： 并行接口
上传时间： 2013-10-25
上传用户：oooool
自制一台ATMEL 89系列FLASH单片机编程器学习单片机最有用的恐怕是编程器和仿真机,一台商品化的编程器至少要几百元,仿真机价格更高,往往让初学者难以选择。这里介绍的一款国外电子网站推出的廉价51编程器，能够读写最常用的12种51单片机，自己动手装配一台，既能锻炼自己的动手能力,又能廉价地装备一台多用编程器，无论是学习单片机或业余时间搞开发，都是一个非常好的选择。笔者按照资料自制了一台，十分好用，不敢独享。特编译了全部制作资料介绍给大家。这个编程器硬件使用标准的ttl系列器件而没有使用特殊元件。它连接在计算机的并行端口，对PC的并口没有特殊要求，所以配置很低的计算机也能用这个编程器。Atmel Flash 系列单片机是当前最流行的单片机，易于擦写，不象OTP芯片容易造成浪费。特别是89系列单片机与大家熟悉的INTEL51系列单片机完全兼容，这个编程器支持的单片机主要是Atmel flash系列。支持的器件： 这个编程器支持以下ATMEL单片机AT89C51,AT89C52,AT89C55,AT89S51,AT89S52,AT89S53,AT89C51RC,AT89C55WD,AT89S8252,AT89C1051U,AT89C2051,AT89C4051注意：20脚的单片机需要一个简单的适配器。（图 2 ） 硬件： 图1显示了这个FLASH 编程器的电路图，编程器和标准的计算机并口连接。电路图中的U2是用于控制计算机和控制器之间的数据流，U4 锁存低位地址字节 ，U5 锁存高位地址字节 ，U3用于产生控制信号给被编程的单片机。IC U1用于产生编程脉冲给单片机.当U7提供编程电压给控制器时，电源部分用U8产生逻辑5v供给。IC U6用于产生5V或6.5V VDD 电源电压给单片机。
上传时间： 2013-10-18
上传用户：bakdesec
