#include <malloc.h> #include <stdio.h> #include <stdlib.h> #include <string.h> #define NULL 0 #define MaxSize 30 typedef struct athletestruct /*运动员*/ { char name[20]; int score; /*分数*/ int range; /**/ int item; /*项目*/ }ATH; typedef struct schoolstruct /*学校*/ { int count; /*编号*/ int serial; /**/ int menscore; /*男选手分数*/ int womenscore; /*女选手分数*/ int totalscore; /*总分*/ ATH athlete[MaxSize]; /**/ struct schoolstruct *next; }SCH; int nsc,msp,wsp; int ntsp; int i,j; int overgame; int serial,range; int n; SCH *head,*pfirst,*psecond; int *phead=NULL,*pafirst=NULL,*pasecond=NULL; void create(); void input () { char answer; head = (SCH *)malloc(sizeof(SCH)); /**/ head->next = NULL; pfirst = head; answer = 'y'; while ( answer == 'y' ) { Is_Game_DoMain: printf("\nGET Top 5 when odd\nGET Top 3 when even"); printf("\n输入运动项目序号 (x<=%d):",ntsp); scanf("%d",pafirst); overgame = *pafirst; if ( pafirst != phead ) { for ( pasecond = phead ; pasecond < pafirst ; pasecond ++ ) { if ( overgame == *pasecond ) { printf("\n这个项目已经存在请选择其他的数字\n"); goto Is_Game_DoMain; } } } pafirst = pafirst + 1; if ( overgame > ntsp ) { printf("\n项目不存在"); printf("\n请重新输入"); goto Is_Game_DoMain; } switch ( overgame%2 ) { case 0: n = 3;break; case 1: n = 5;break; } for ( i = 1 ; i <= n ; i++ ) { Is_Serial_DoMain: printf("\n输入序号 of the NO.%d (0<x<=%d): ",i,nsc); scanf("%d",&serial); if ( serial > nsc ) { printf("\n超过学校数目,请重新输入"); goto Is_Serial_DoMain; } if ( head->next == NULL ) { create(); } psecond = head->next ; while ( psecond != NULL ) { if ( psecond->serial == serial ) { pfirst = psecond; pfirst->count = pfirst->count + 1; goto Store_Data; } else { psecond = psecond->next; } } create(); Store_Data: pfirst->athlete[pfirst->count].item = overgame; pfirst->athlete[pfirst->count].range = i; pfirst->serial = serial; printf("Input name:) : "); scanf("%s",pfirst->athlete[pfirst->count].name); } printf("\n继续输入运动项目(y&n)？"); answer = getchar(); printf("\n"); } } void calculate() /**/ { pfirst = head->next; while ( pfirst->next != NULL ) { for (i=1;i<=pfirst->count;i++) { if ( pfirst->athlete[i].item % 2 == 0 ) { switch (pfirst->athlete[i].range) { case 1:pfirst->athlete[i].score = 5;break; case 2:pfirst->athlete[i].score = 3;break; case 3:pfirst->athlete[i].score = 2;break; } } else { switch (pfirst->athlete[i].range) { case 1:pfirst->athlete[i].score = 7;break; case 2:pfirst->athlete[i].score = 5;break; case 3:pfirst->athlete[i].score = 3;break; case 4:pfirst->athlete[i].score = 2;break; case 5:pfirst->athlete[i].score = 1;break; } } if ( pfirst->athlete[i].item <=msp ) { pfirst->menscore = pfirst->menscore + pfirst->athlete[i].score; } else { pfirst->womenscore = pfirst->womenscore + pfirst->athlete[i].score; } } pfirst->totalscore = pfirst->menscore + pfirst->womenscore; pfirst = pfirst->next; } } void output() { pfirst = head->next; psecond = head->next; while ( pfirst->next != NULL ) { // clrscr(); printf("\n第%d号学校的结果成绩:",pfirst->serial); printf("\n\n项目的数目\t学校的名字\t分数"); for (i=1;i<=ntsp;i++) { for (j=1;j<=pfirst->count;j++) { if ( pfirst->athlete[j].item == i ) { printf("\n %d\t\t\t\t\t\t%s\n %d",i,pfirst->athlete[j].name,pfirst->athlete[j].score);break; } } } printf("\n\n\n\t\t\t\t\t\t按任意建 进入下一页"); getchar(); pfirst = pfirst->next; } // clrscr(); printf("\n运动会结果:\n\n学校编号\t男运动员成绩\t女运动员成绩\t总分"); pfirst = head->next; while ( pfirst->next != NULL ) { printf("\n %d\t\t %d\t\t %d\t\t %d",pfirst->serial,pfirst->menscore,pfirst->womenscore,pfirst->totalscore); pfirst = pfirst->next; } printf("\n\n\n\t\t\t\t\t\t\t按任意建结束"); getchar(); } void create() { pfirst = (struct schoolstruct *)malloc(sizeof(struct schoolstruct)); pfirst->next = head->next ; head->next = pfirst ; pfirst->count = 1; pfirst->menscore = 0; pfirst->womenscore = 0; pfirst->totalscore = 0; } void Save() {FILE *fp; if((fp = fopen("school.dat","wb"))==NULL) {printf("can't open school.dat\n"); fclose(fp); return; } fwrite(pfirst,sizeof(SCH),10,fp); fclose(fp); printf("文件已经成功保存\n"); } void main() { system("cls"); printf("\n\t\t\t 运动会分数统计\n"); printf("输入学校数目 (x>= 5):"); scanf("%d",&nsc); printf("输入男选手的项目(x<=20):"); scanf("%d",&msp); printf("输入女选手项目(<=20):"); scanf("%d",&wsp); ntsp = msp + wsp; phead = (int *)calloc(ntsp,sizeof(int)); pafirst = phead; pasecond = phead; input(); calculate(); output(); Save(); }
标签： 源代码
上传时间： 2016-12-28
上传用户：150501
The writing of this book was prompted by two main developments in wireless communications in the past decade. First is the huge surge of research activities in physical-layer wireless communication theory. While this has been a subject of study since the 60’s, recent developments in the field, such as opportunistic and multi-input multi-output (MIMO) communication techniques, have brought completely new per- spectives on how to communicate over wireless channels.
标签： Communication Fundamentals Wireless of
上传时间： 2020-05-27
上传用户：shancjb
An acronym for Multiple-In, Multiple-Out, MIMO communication sends the same data as several signals simultaneously through multiple antennas, while still utilizing a single radio channel. This is a form of antenna diversity, which uses multiple antennas to improve signal quality and strength of an RF link. The data is split into multiple data streams at the transmission point and recombined on the receive side by another MIMO radio configured with the same number of antennas. The receiver is designed to take into account the slight time difference between receptions of each signal, any additional noise or interference, and even lost signals.
标签： Understanding_the_Basics_of_MIMO
上传时间： 2020-06-01
上传用户：shancjb
FPGA采样AD9238数据并通过VGA波形显示例程 Verilog逻辑源码Quartus工程文件+文档说明,FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。ADC 模块型号为 AN9238，最大采样率 65Mhz，精度为12 位。实验中把 AN9238 的 2 路输入以波形方式在 HDMI 上显示出来，我们可以用更加直观的方式观察波形，是一个数字示波器雏形。module top( input clk, input rst_n, output ad9238_clk_ch0, output ad9238_clk_ch1, input[11:0] ad9238_data_ch0, input[11:0] ad9238_data_ch1, //vga output output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b //vga blue);wire video_clk;wire video_hs;wire video_vs;wire video_de;wire[7:0] video_r;wire[7:0] video_g;wire[7:0] video_b;wire grid_hs;wire grid_vs;wire grid_de;wire[7:0] grid_r;wire[7:0] grid_g;wire[7:0] grid_b;wire wave0_hs;wire wave0_vs;wire wave0_de;wire[7:0] wave0_r;wire[7:0] wave0_g;wire[7:0] wave0_b;wire wave1_hs;wire wave1_vs;wire wave1_de;wire[7:0] wave1_r;wire[7:0] wave1_g;wire[7:0] wave1_b;wire adc_clk;wire adc0_buf_wr;wire[10:0] adc0_buf_addr;wire[7:0] adc0_bu
上传时间： 2021-10-27
上传用户：qingfengchizhu
FPGA读写SD卡读取BMP图片通过LCD显示例程实验 Verilog逻辑源码Quartus工程文件+文档说明,FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。1 实验简介在前面的实验中我们练习了 SD 卡读写，VGA 视频显示等例程，本实验将 SD 卡里的 BMP 图片读出，写入到外部存储器，再通过 VGA、LCD 等显示。本实验如果通过液晶屏显示，需要有液晶屏模块。2 实验原理在前面的实验中我们在 VGA、LCD 上显示的是彩条，是 FPGA 内部产生的数据，本实验将彩条替换为 SD 内的 BMP 图片数据，但是 SD 卡读取速度远远不能满足显示速度的要求，只能先写入外部高速 RAM，再读出后给视频时序模块显示module top( input clk, input rst_n, input key1, output [5:0] seg_sel, output [7:0] seg_data, output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sd_ncs, //SD card chip select (SPI mode) output sd_dclk, //SD card clock output sd_mosi, //SD card controller data output input sd_miso, //SD card controller data input output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24
标签： fpga
上传时间： 2021-10-27
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FPGA读取OV5640摄像头数据并通过VGA或LCD屏显示输出的Verilog逻辑源码Quartus工程文件+文档说明，FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。module top( input clk, input rst_n, output cmos_scl, //cmos i2c clock inout cmos_sda, //cmos i2c data input cmos_vsync, //cmos vsync input cmos_href, //cmos hsync refrence,data valid input cmos_pclk, //cmos pxiel clock output cmos_xclk, //cmos externl clock input [7:0] cmos_db, //cmos data output cmos_rst_n, //cmos reset output cmos_pwdn, //cmos power down output vga_out_hs, //vga horizontal synchronization output vga_out_vs, //vga vertical synchronization output[4:0] vga_out_r, //vga red output[5:0] vga_out_g, //vga green output[4:0] vga_out_b, //vga blue output sdram_clk, //sdram clock output sdram_cke, //sdram clock enable output sdram_cs_n, //sdram chip select output sdram_we_n, //sdram write enable output sdram_cas_n, //sdram column address strobe output sdram_ras_n, //sdram row address strobe output[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank address output[12:0] sdram_addr, //sdram address inout[15:0] sdram_dq //sdram data);
上传时间： 2021-12-18
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基于FPGA设计的sdram读写测试实验Verilog逻辑源码Quartus工程文件+文档说明，DRAM选用海力士公司的 HY57V2562 型号,容量为的 256Mbit,采用了 54 引脚的TSOP 封装, 数据宽度都为 16 位, 工作电压为 3.3V,并丏采用同步接口方式所有的信号都是时钟信号。FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ps/1psmodule top(input clk,input rst_n,output[1:0] led,output sdram_clk, //sdram clockoutput sdram_cke, //sdram clock enableoutput sdram_cs_n, //sdram chip selectoutput sdram_we_n, //sdram write enableoutput sdram_cas_n, //sdram column address strobeoutput sdram_ras_n, //sdram row address strobeoutput[1:0] sdram_dqm, //sdram data enable output[1:0] sdram_ba, //sdram bank addressoutput[12:0] sdram_addr, //sdram addressinout[15:0] sdram_dq //sdram data);parameter MEM_DATA_BITS = 16 ; //external memory user interface data widthparameter ADDR_BITS = 24 ; //external memory user interface address widthparameter BUSRT_BITS = 10 ; //external memory user interface burst widthparameter BURST_SIZE = 128 ; //burst sizewire wr_burst_data_req; // from external memory controller,write data request ,before data 1 clockwire wr_burst_finish; // from external memory controller,burst write finish
标签： fpga sdram verilog quartus
上传时间： 2021-12-18
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ADS8329 Verilog fpga 驱动源码，2.7V 至 5.5V 16 位 1MSPS 串行模数转换器 ADC芯片ADS8329数据采集的verilog代码，已经用在工程中，可以做为你的设计参考。( input clock, input timer_clk_r, input reset, output reg sample_over, output reg ad_convn, input ad_eocn, output reg ad_csn, output reg ad_clk, input ad_dout, output reg ad_din, output reg [15:0] ad_data_lock);reg [15:0] ad_data_old;reg [15:0] ad_data_new; reg [19:0] ad_data_temp; reg [15:0] ad_data;reg [4:0] ad_data_cnt;reg [4:0] ad_spi_cnt; reg [5:0] time_dly_cnt; parameter [3:0] state_mac_IDLE = 0, state_mac_0 = 1, state_mac_1 = 2, state_mac_2 = 3, state_mac_3 = 4, state_mac_4 = 5, state_mac_5 = 6, state_mac_6 = 7, state_mac_7 = 8, state_mac_8 = 9, state_mac_9 = 10, state_mac_10 = 11, state_mac_11 = 12, state_mac_12 = 13, state_mac_13 = 14, state_mac_14 = 15; reg [3:0] state_curr;reg [3:0] state_next;
上传时间： 2022-01-30
上传用户：1208020161
Precision, Low Noise, CMOS, Rail-to-Rail, Input/Output Operational Amplifiers Data Sheet AD8605/AD8606/AD8608The AD8605, AD8606, and AD86081 are single, dual, and quad rail-to-rail input and output, single-supply amplifiers. They feature very low offset voltage, low input voltage and current noise, and wide signal bandwidth. They use the Analog Devices, Inc. patented DigiTrim® trimming technique, which achieves
标签： 运算放大器
上传时间： 2022-02-02
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spi 通信的master部分使用的verilog语言实现，可以做为你的设计参考。module spi_master(rstb,clk,mlb,start,tdat,cdiv,din, ss,sck,dout,done,rdata); input rstb,clk,mlb,start; input [7:0] tdat; //transmit data input [1:0] cdiv; //clock divider input din; output reg ss; output reg sck; output reg dout; output reg done; output reg [7:0] rdata; //received dataparameter idle=2'b00; parameter send=2'b10; parameter finish=2'b11; reg [1:0] cur,nxt; reg [7:0] treg,rreg; reg [3:0] nbit; reg [4:0] mid,cnt; reg shift,clr;
上传时间： 2022-02-03
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