iic总线控制器VHDL实现 -- VHDL Source Files: i2c.vhd -- top level file i2c_control.vhd -- control function for the I2C master/slave shift.vhd -- shift register uc_interface.vhd -- uC interface function for an 8-bit 68000-like uC upcnt4.vhd -- 4-bit up counter i2c_timesim.vhd -- post-route I2C simulation netlist
标签： VHDL c_control vhd control
上传时间： 2016-10-30
上传用户：woshiayin
KNN K-nearest neighbor rule for classification
标签： classification K-nearest neighbor rule
上传时间： 2016-10-30
上传用户：yangbo69
K-means clustering using Berkeley DB
标签： clustering Berkeley K-means using
上传时间： 2013-12-01
上传用户：caozhizhi
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上传时间： 2013-12-13
上传用户：himbly
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上传时间： 2014-01-20
上传用户：三人用菜
介绍了基于Altera 公司的CPLD 芯片FL EX10 K,以及利用VHDL 语言实现多位二进 制码转换成8421BCD 码的原理、设计思路和软件实现。
上传时间： 2016-11-03
上传用户：manking0408
一个关于k最近临法分类的matlab程序
上传时间： 2014-01-19
上传用户：CHENKAI
K-mean算法，并通过了IRIS数据的测试。
上传时间： 2013-12-18
上传用户：shawvi
基于matlab的K均值聚类程序。其中用IRIS数据进行验证，得到了很好的结果。文件中包含了演示后的结果图
上传时间： 2014-01-21
上传用户：lizhizheng88
对一个50个结点（更多的节点的网络只需要修改模块中的标量维数就行）的复杂非线性耦合网络进行同步化仿真。首先生成K矩阵，然后运行simulink，即可得到50个洛仑兹混沌节点复杂网络的同步化曲线。
上传时间： 2014-01-14
上传用户：lyy1234
