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  • This manual describes SAMSUNG s S3C2410X 16/32-bit RISC microprocessor. This product is designed to

    This manual describes SAMSUNG s S3C2410X 16/32-bit RISC microprocessor. This product is designed to provide hand-held devices and general applications with cost-effective, low-power, and high-performance microcontroller solution in small die size. To reduce total system cost, the S3C2410X includes the following components separate 16KB Instruction and 16KB Data Cache, MMU to handle virtual memory management, LCD Controller (STN & TFT), NAND Flash Boot Loader, System Manager (chip select logic and SDRAM Controller), 3-ch UART, 4-ch DMA, 4-ch Timers with PWM, I/O Ports, RTC, 8-ch 10-bit ADC and Touch Screen Interface, IIC-BUS Interface, IIS-BUS Interface, USB Host, USB Device, SD Host & Multi-Media Card Interface, 2-ch SPI and PLL for clock generation.

    标签: This microprocessor describes S3C2410X

    上传时间: 2014-01-11

    上传用户:shizhanincc

  • Quake 3 s MD3 Viewer (july 13, 2007), loads and displays a player and a weapon. Supports lighting,

    Quake 3 s MD3 Viewer (july 13, 2007), loads and displays a player and a weapon. Supports lighting, texture mapping and animation. Includes a sample player model with weapon. See README for how to use it. Note (1): it uses the POSIX opendir/readdir functions, which are not implemented in all compilers under Windows (MinGW supports them). Note (2): This demo works on little endian architectures only. Libraries: OpenGL, GLU, GLUT, boost, libjpeg. Files: md3loader.zip (2.4 MB)

    标签: and Supports displays lighting

    上传时间: 2017-09-10

    上传用户:czl10052678

  • FPGA的多路可控脉冲延迟系统.docx

     1  系统功能   本系统拟定对频率范围在1~50 kHz左右的TTL电平脉冲序列进行多路延迟处理。各路延迟时间分别由单片机动态设定,最大延迟时间为1 ms,最大分辨率为0.15 ns级。  3  方案实现   系统选用Actel公司的ProASIC3 A3P250芯片实现数字部分。系统时钟由外部50 MHz晶振提供,时钟引脚连接到FPGA的CCC全局时钟引脚上;频率可以通过FPGA内部的PLL实现倍频和分频,设定需要的频率。由于在多路脉冲延迟方案中电路的同步是保证控制正确的条件,所以应该首先为电路提供一个基准脉冲。

    标签: FPGA的多路可控脉冲延迟

    上传时间: 2015-04-25

    上传用户:justgo123

  • 振荡电路的设计与应用

    《振荡电路的设计与应用》主要介绍振荡电路的设计与应用,内容包括基本振荡电路、RC方波振荡电路的设计、RC正弦波振荡电路的设计、高频LC振荡电路的设计、陶瓷与晶体振荡电路的设计,以及函数发生器的设计、电压控制振荡电路的设计、PLL频率合成器的设计、数字频率合成器的设计,等等

    标签: 震荡 模拟

    上传时间: 2016-01-21

    上传用户:byhejun

  • tas3204

    The TAS3204 is a highly-integrated audio system-on-chip (SOC) consisting of a fully-programmable, 48-bit digital audio processor, a 3:1 stereo analog input MUX, four ADCs, four DACs, and other analog functionality. The TAS3204 is programmable with the graphical PurePath Studio™ suite of DSP code development software. PurePath Studio is a highly intuitive, drag-and-drop environment that minimizes software development effort while allowing the end user to utilize the power and flexibility of the TAS3204’s digital audio processing core. TAS3204 processing capability includes speaker equalization and crossover, volume/bass/treble control, signal mixing/MUXing/splitting, delay compensation, dynamic range compression, and many other basic audio functions. Audio functions such as matrix decoding, stereo widening, surround sound virtualization and psychoacoustic bass boost are also available with either third-party or TI royalty-free algorithms. The TAS3204 contains a custom-designed, fully-programmable 135-MHz, 48-bit digital audio processor. A 76-bit accumulator ensures that the high precision necessary for quality digital audio is maintained during arithmetic operations. Four differential 102 dB DNR ADCs and four differential 105 dB DNR DACs ensure that high quality audio is maintained through the whole signal chain as well as increasing robustness against noise sources such as TDMA interference. The TAS3204 is composed of eight functional blocks: Clocking System Digital Audio Interface Analog Audio Interface Power supply Clocks, digital PLL I2C control interface 8051 MCUcontroller Audio DSP – digital audio processing 特性 Digital Audio Processor Fully Programmable With the Graphical, Drag-and-Drop PurePath Studio™ Software Development Environment 135-MHz Operation 48-Bit Data Path With 76-Bit Accumulator Hardware Single-Cycle Multiplier (28 × 48)

    标签: 3204 tas

    上传时间: 2016-05-06

    上传用户:fagong

  • Phase Locked Loop Design Fundamentals

    描述 了PLL 的基础知识哦,非常的 实用

    标签: Phase Locked Loop Design Fundamentals

    上传时间: 2017-03-13

    上传用户:rfzhangyicheng

  • pll for high frequency receivers and transmitters

    ADI公司的引用笔记,讲解了锁相环在通信接收机和发射机的应用

    标签: transmitters frequency receivers high pll for and

    上传时间: 2017-03-13

    上传用户:rfzhangyicheng

  • 二阶锁相环

    采用MATLAB仿真二阶锁相环PLL,仿真环境MATLAB R2016a,包括源码等

    标签: 二阶 锁相环

    上传时间: 2018-03-28

    上传用户:auheish

  • MIMO-OFDM Wireless Communications with MATLAB

    MIMO-OFDM is a key technology for next-generation cellular communications (3GPP-LTE, Mobile WiMAX, IMT-Advanced) as well as wireless LAN (IEEE 802.11a, IEEE 802.11n), wireless PAN (MB-OFDM), and broadcasting (DAB, DVB, DMB). This book provides a comprehensive introduction to the basic theory and practice of wireless channel modeling, OFDM, and MIMO, with MATLAB ? programs to simulate the underlying techniques on MIMO-OFDMsystems.Thisbookisprimarilydesignedforengineersandresearcherswhoare interested in learning various MIMO-OFDM techniques and applying them to wireless communications.

    标签: Communications MIMO-OFDM Wireless MATLAB with

    上传时间: 2020-05-28

    上传用户:shancjb

  • Optical+Communication+Theory+and+Techniques

    Since the advent of optical communications, a great technological effort has been devoted to the exploitation of the huge bandwidth of optical fibers. Start- ing from a few Mb/s single channel systems, a fast and constant technological development has led to the actual 10 Gb/s per channel dense wavelength di- vision multiplexing (DWDM) systems, with dozens of channels on a single fiber. Transmitters and receivers are now ready for 40 Gb/s, whereas hundreds of channels can be simultaneously amplified by optical amplifiers.

    标签: Communication Techniques Optical Theory and

    上传时间: 2020-05-31

    上传用户:shancjb