This Verilog HDL description implements a UART Version 1.1 : Original Creation 2.1 : added commen
This Verilog HDL description implements a UART Version 1.1 : Original Creation 2.1 : added comments...
This Verilog HDL description implements a UART Version 1.1 : Original Creation 2.1 : added comments...
基于Verilog-HDL的转子振动噪声电压峰值检测,值得学习啊,...
(219)卷积编码的verilog hdl源代码,很有用的啊,...
适合高速Viterbi译码器的hdl的设计与实现...
用VERILOG HDL实现的任意 频率分频器源代码,是一个通用的程序...