FPGA片内FIFO读写测试Verilog逻辑源码Quartus工程文件+文档说明，使用 FPGA 内部的 FIFO 以及程序对该 FIFO 的数据读写操作。FPGA型号Cyclone4E系列中的EP4CE6F17C8，Quartus版本17.1。timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////module fifo_test( input clk, //50MHz时钟 input rst_n //复位信号，低电平有效 );//-----------------------------------------------------------localparam W_IDLE = 1;localparam W_FIFO = 2; localparam R_IDLE = 1;localparam R_FIFO = 2; reg[2:0] write_state;reg[2:0] next_write_state;reg[2:0] read_state;reg[2:0] next_read_state;reg[15:0] w_data; //FIFO写数据wire wr_en; //FIFO写使能wire rd_en; //FIFO读使能wire[15:0] r_data; //FIFO读数据wire full; //FIFO满信号 wire empty; //FIFO空信号 wire[8:0] rd_data_count; wire[8:0] wr_data_count; ///产生FIFO写入的数据always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) write_state <= W_IDLE; else write_state <= next_write_state;endalways@(*)begin case(write_state) W_IDLE: if(empty == 1'b1) //FIFO空， 开始写FIFO next_write_state <= W_FIFO; else next_write_state <= W_IDLE; W_FIFO: if(full == 1'b1) //FIFO满 next_write_state <= W_IDLE; else next_write_state <= W_FIFO; default: next_write_state <= W_IDLE; endcaseendassign wr_en = (next_write_state == W_FIFO) ? 1'b1 : 1'b0; always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) w_data <= 16'd0; else if (wr_en == 1'b1) w_data <= w_data + 1'b1; else w_data <= 16'd0; end///产生FIFO读的数据always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) read_state <= R_IDLE; else read_state <= next_read_state;endalways@(*)begin case(read_state) R_IDLE: if(full == 1'b1) //FIFO满, 开始读FIFO next_read_state <= R_FIFO; else next_read_state <= R_IDLE; R_FIFO: if(empty == 1'b1)
上传时间： 2021-12-19
上传用户：20125101110
1. Scope ......................................................................................................................................................................... 12. DDR4 SDRAM Package Pinout and Addressing ....................................................................................................... 22.1 DDR4 SDRAM Row for X4,X8 and X16 ................................................................................................................22.2 DDR4 SDRAM Ball Pitch........................................................................................................................................22.3 DDR4 SDRAM Columns for X4,X8 and X16 ..........................................................................................................22.4 DDR4 SDRAM X4/8 Ballout using MO-207......................................................................................................... 22.5 DDR4 SDRAM X16 Ballout using MO-207.............................................................................................................32.6 Pinout Description ..................................................................................................................................................52.7 DDR4 SDRAM Addressing.....................................................................................................................................73. Functional Description ...............................................................................................................................................83.1 Simplified State Diagram ....................................................................................................................................83.2 Basic Functionality..................................................................................................................................................93.3 RESET and Initialization Procedure .....................................................................................................................103.3.1 Power-up Initialization Sequence .............................................................................................................103.3.2 Reset Initialization with Stable Power ......................................................................................................113.4 Register Definition ................................................................................................................................................123.4.1 Programming the mode registers .............................................................................................................123.5 Mode Register ......................................................................................................................................................134. DDR4 SDRAM Command Description and Operation ............................................................................................. 244.1 Command Truth Table ..........................................................................................................................................244.2 CKE Truth Table ...................................................................................................................................................254.3 Burst Length, Type and Order ..............................................................................................................................264.3.1 BL8 Burst order with CRC Enabled .........................................................................................................264.4 DLL-off Mode & DLL on/off Switching procedure ................................................................................................274.4.1 DLL on/off switching procedure ...............................................................................................................274.4.2 DLL “on” to DLL “off” Procedure ..............................................................................................................274.4.3 DLL “off” to DLL “on” Procedure ..............................................................................................................284.5 DLL-off Mode........................................................................................................................................................294.6 Input Clock Frequency Change ............................................................................................................................304.7 Write Leveling.......................................................................................................................................................314.7.1 DRAM setting for write leveling & DRAM termination function in that mode ............................................324.7.2 Procedure Description .............................................................................................................................334.7.3 Write Leveling Mode Exit .........................................................................................................................34
标签： DDR4
上传时间： 2022-01-09
上传用户：
Keil激活_Keygen-Decompressed-Full-2030.zip
标签： Keil
上传时间： 2022-01-28
上传用户：
The PW3130 series product is a high integration solution for lithium-lion/polymer batteryprotection.PW3130 contains advanced power MOSFET, high-accuracy voltage detection circuits anddelay circuits. PW3130 is put into an ultra-small SOT23-5 package and only one external componentmakes it an ideal solution in limited space of battery pack. PW3130 has all the protection functionsrequired in the battery application including overcharging, overdischarging, overcurrent and loadshort circuiting protection etc. The accurate overcharging detection voltage ensures safe and fullutilization charging.The low standby current drains little current from the cell while in storage. Thedevice is not only targeted for digital cellular phones, but also for any other Li-Ion and Li-Polybattery-powered information appliances requiring long-term battery life
标签： pw3130
上传时间： 2022-02-11
上传用户：fliang
InGaAs/AlGaAs semiconductor lasers come in threetypes: VCSELs and two types of EELs. The VCSEL, asits name implies, emits vertically, normal to the planeof the device, owing to cavity mirrors grown withinthe epitaxial material itself. The VCSEL’s circular beamhas a numerical aperture (NA) of roughly 0.2, or a fullangle of approximately 25 degrees.
标签： tof
上传时间： 2022-02-12
上传用户：
本书是 Marc Thompson 博士 20 年模拟电路设计和教学经验的总结，讲述了模拟电路与系统设计中常用的直观分析方法。本书提出了“模拟电路直观方法学”，力图帮助学生和设计人员摆脱复杂的理论推导与计算，充分利用直观知识来应对模拟电路工程设计挑战。全书共分为 16 章，内容涵盖了二极管、晶体管、放大器、滤波器、反馈系统等模拟电路的基本知识与设计方法。本书大纲第 1 章与第 2 章为介绍性材料。第 1 章是本书的引言，同时介绍了模拟电路设计的发展动机，其中引用了一些精选的历史事件。第 2 章讲述后续章节中用到地重要的信号处理概念，以使读者们能够跟上作者的思路。第 3 章至第 8 章讲述双极性器件的物理学原理、双极性结型晶体管 (bipolar junction transistor, BJT) 、晶体管放大器，以及用于带宽估计与开关速度分析的近似技术。第 9 章讲述 CMOS 管和 CMOS 管放大器的基础知识。前面章节介绍的用于放大器设计的带宽估计技术也同样适用于 CMOS 管器件。第 10 章讲述 晶体管的开关效应。晶体管是如何实现导通和关闭呢？又如何估计它的开关速度呢？第 11 章回顾反馈系统 (feedback system) 的基本知识以及设计稳定反馈系统的伯德图 / 相位裕度方法 (Bod plot / phase margin) 。第 12 章和第 13 章讲述实际运算放大器的设计、使用和限制，包括电压反馈 (voltage-feedback) 以及电流反馈 (current-feedback) 放大器。第 14 章讲述模拟低通滤波器设计的基本知识，包括巴特沃思 (Butterworth) 、切比雪夫 (Chebyshev) 、椭圆 (elliptic) 以及贝塞尔 (Bessel) 滤波器的无源梯形实现和胡源实现。第 15 章讲述实际电路设计问题，比如 PCB 版图设计规则、无源器件的使用和限制等。第 16 章是一些有用的设计技术和设计技巧的大杂烩，这些内容又不适合放在其他章节，所以作为独立的章节进行讲述。一些说明性的分析问题以及 MATLAB 和 SPICE 设计示例点缀在全书的字里行间，以帮助读者理解本书的内容。
标签： 模拟电路
上传时间： 2022-02-14
上传用户：
The PW2053 is a high-efficiency monolithic synchronous buck regulator using a constantfrequency, current mode architecture. The device is available in an adjustable version. Supply currentwith no load is 40uA and drops to <1uA in shutdown. The 2.5V to 5.5V input voltage range makesthe PW2053 ideally suited for single Li-Ion battery powered applications. 100% duty cycle provideslow dropout operation, extending battery life in portable systems. PWM/PFM mode operationprovides very low output ripple voltage for noise sensitive applications. Switching frequency isinternally set at 1.2MHz, allowing the use of small surface mount inductors and capacitors. Lowoutput voltages are easily supported with the 0.6V feedback reference voltage
标签： pw2053
上传时间： 2022-02-14
上传用户：jason_vip1
The PW8205A8TS is the highest performance trench N-ch MOSFETs with extreme high cell density,which provide excellent RDSON and gate charge for most of the small power switching and loadswitch applications. The meet the RoHS and Product requirement with full function reliabilityapproved .
标签： 8205a8
上传时间： 2022-02-14
上传用户：wangshoupeng199
Single chip TFT-LCD Controller/Driver with On-chip Frame Memory (FM) Display Resolution: 240*RGB (H) *320(V) Frame Memory Size: 240 x 320 x 18-bit = 1,382,400 bits LCD Driver Output Circuits- Source Outputs: 240 RGB Channels- Gate Outputs: 320 Channels- Common Electrode Output Display Colors (Color Mode)- Full Color: 262K, RGB=(666) max., Idle Mode Off- Color Reduce: 8-color, RGB=(111), Idle Mode On Programmable Pixel Color Format (Color Depth) for Various Display Data input Format- 12-bit/pixel: RGB=(444)- 16-bit/pixel: RGB=(565)- 18-bit/pixel: RGB=(666) MCU Interface- Parallel 8080-series MCU Interface (8-bit, 9-bit, 16-bit & 18-bit)- 6/16/18 RGB Interface(VSYNC, HSYNC, DOTCLK, ENABLE, DB[17:0])- Serial Peripheral Interface(SPI Interface)- VSYNC Interface
上传时间： 2022-03-04
上传用户：
目前电动汽车主要以锂电池作为动力来源,为了提高锂电池的使用时间和安全性,为锂电池提供安全良好的运行环境,电池管理系统应运而生。BMS主控单元基于S32K144汽车级单片机,通过主从式网络控制结构能够对锂电池的各个参数进行采集与分析。采用扩展卡尔曼滤波对电池的荷电状态(SOC)进行估算,克服普通估算方法无法避免电池内阻误差的缺点,通过Matlab/Simulink软件仿真验证可使估算误差达到2%以内。At present,electric vehicles mainly use lithium batteries as the power source.In order to improve the running time and safety of lithium batteries,a safe and good operating environment for power batteries is provided,and a battery management system(BMS) has emerged.The BMS main control unit is based on the S32K144 automotive-grade control chip.Through the master-slave network control structure,it can collect and analyze the various parameters of the lithium battery.The Extended Kalman Filter(EKF) is used to estimate the state of charge(SOC) of the battery,which overcomes the shortcomings of the internal estimation method that cannot overcome the internal resistance error of the battery.It can be verified by Matlab/Simulink software simulation.The estimation error is within 2%.
上传时间： 2022-03-26
上传用户：XuVshu
