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  • Auto-Machine-Learning-Methods-Systems-Challenges

    The past decade has seen an explosion of machine learning research and appli- cations; especially, deep learning methods have enabled key advances in many applicationdomains,suchas computervision,speechprocessing,andgameplaying. However, the performance of many machine learning methods is very sensitive to a plethora of design decisions, which constitutes a considerable barrier for new users. This is particularly true in the booming field of deep learning, where human engineers need to select the right neural architectures, training procedures, regularization methods, and hyperparameters of all of these components in order to make their networks do what they are supposed to do with sufficient performance. This process has to be repeated for every application. Even experts are often left with tedious episodes of trial and error until they identify a good set of choices for a particular dataset.

    标签: Auto-Machine-Learning-Methods-Sys tems-Challenges

    上传时间: 2020-06-10

    上传用户:shancjb

  • Autonomous+Robots+Modeling,+Path+Planning

    A kinematically redundant manipulator is a serial robotic arm that has more independently driven joints than are necessary to define the desired pose (position and orientation) of its end-effector. With this definition, any planar manipulator (a manipulator whose end-effector motion is restrained in a plane) with more than three joints is a redundant manipulator. Also, a manipulator whose end-effector can accept aspatialposeisaredundant manipulator ifithas morethan sixindependently driven joints. For example, the manipulator shown in Fig. 1.1 has two 7-DOF arms mounted on a torso with three degrees of freedom (DOFs). This provides 10 DOFs for each arm. Since the end-effector of each arm can have a spatial motion with six DOFs, the arms are redundant.

    标签: Autonomous Modeling Planning Robots Path

    上传时间: 2020-06-10

    上传用户:shancjb

  • Embedded_Deep_Learning_-_Algorithms

    Although state of the art in many typical machine learning tasks, deep learning algorithmsareverycostly interms ofenergyconsumption,duetotheirlargeamount of required computations and huge model sizes. Because of this, deep learning applications on battery-constrained wearables have only been possible through wireless connections with a resourceful cloud. This setup has several drawbacks. First, there are privacy concerns. Cloud computing requires users to share their raw data—images, video, locations, speech—with a remote system. Most users are not willing to do this. Second, the cloud-setup requires users to be connected all the time, which is unfeasible given current cellular coverage. Furthermore, real-time applications require low latency connections, which cannot be guaranteed using the current communication infrastructure. Finally, wireless connections are very inefficient—requiringtoo much energyper transferredbit for real-time data transfer on energy-constrained platforms.

    标签: Embedded_Deep_Learning Algorithms

    上传时间: 2020-06-10

    上传用户:shancjb

  • TI DC-2G采样 50-Ohm Oscilloscope Front-end Design

    TI高速AD采样系统设计原理图 DC 2G

    标签: 采样系统

    上传时间: 2021-10-30

    上传用户:

  • 1 Seismic response control using electromagnetic

    This paper presents a new type of electromagnetic damper with rotating inertial mass that has been devel oped to control the vibrations of structures subjected to earthquakes. The electromagnetic inertial mass damper (EIMD) consists of a ball screw that converts axial oscillation of the rod end into rotational motion of the internal flflywheel and an electric generator that is turned by the rotation of the inner rod. The EIMD is able to generate a large inertial force created by the rotating flflywheel and a variable damping force devel oped by the electric generator. Device performance tests of reduced-scale and full-scale EIMDs were under taken to verify the basic characteristics of the damper and the validity of the derived theoretical formulae. Shaking table tests of a three-story structure with EIMDs and earthquake response analyses of a building with EIMDs were conducted to demonstrate the seismic response control performance of the EIMD. The EIMD is able to reduce story drifts as well as accelerations and surpasses conventional types of dampers in reducing acceleration responses.

    标签: electromagnetic response Seismic control using

    上传时间: 2021-11-04

    上传用户:a1293065

  • IEEE_Verilog_2001

    The Verilog Hardware Description Language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine readable and human readable,it supports the development,verification, synthesis,and testing of hardware designs; the communication of hardware design data; and the maintenance,modification,and procurement of hardware. The primary audiences for this standard are the implementors of tools supporting the language and advanced users of the language.

    标签: ieee verilog

    上传时间: 2021-11-09

    上传用户:

  • FPGA片内FIFO读写测试Verilog逻辑源码Quartus工程文件+文档说明 使用 FPGA

    FPGA片内FIFO读写测试Verilog逻辑源码Quartus工程文件+文档说明,使用 FPGA 内部的 FIFO 以及程序对该 FIFO 的数据读写操作。FPGA型号Cyclone4E系列中的EP4CE6F17C8,Quartus版本17.1。timescale 1ns / 1ps//////////////////////////////////////////////////////////////////////////////////module fifo_test( input clk,           //50MHz时钟 input rst_n              //复位信号,低电平有效 );//-----------------------------------------------------------localparam      W_IDLE      = 1;localparam      W_FIFO     = 2; localparam      R_IDLE      = 1;localparam      R_FIFO     = 2; reg[2:0]  write_state;reg[2:0]  next_write_state;reg[2:0]  read_state;reg[2:0]  next_read_state;reg[15:0] w_data;    //FIFO写数据wire      wr_en;    //FIFO写使能wire      rd_en;    //FIFO读使能wire[15:0] r_data; //FIFO读数据wire       full;  //FIFO满信号 wire       empty;  //FIFO空信号 wire[8:0]  rd_data_count;  wire[8:0]  wr_data_count;  ///产生FIFO写入的数据always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) write_state <= W_IDLE; else write_state <= next_write_state;endalways@(*)begin case(write_state) W_IDLE: if(empty == 1'b1)               //FIFO空, 开始写FIFO next_write_state <= W_FIFO; else next_write_state <= W_IDLE; W_FIFO: if(full == 1'b1)                //FIFO满 next_write_state <= W_IDLE; else next_write_state <= W_FIFO; default: next_write_state <= W_IDLE; endcaseendassign wr_en = (next_write_state == W_FIFO) ? 1'b1 : 1'b0; always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) w_data <= 16'd0; else    if (wr_en == 1'b1)     w_data <= w_data + 1'b1; else          w_data <= 16'd0; end///产生FIFO读的数据always@(posedge clk or negedge rst_n)begin if(rst_n == 1'b0) read_state <= R_IDLE; else read_state <= next_read_state;endalways@(*)begin case(read_state) R_IDLE: if(full == 1'b1)               //FIFO满, 开始读FIFO next_read_state <= R_FIFO; else next_read_state <= R_IDLE; R_FIFO: if(empty == 1'b1)   

    标签: fpga fifo verilog quartus

    上传时间: 2021-12-19

    上传用户:20125101110

  • LTC2756 18位乘法串行输入电流输出数模转换器DAC模块ALTIUM原理图+PCB文件

    LTC2756 18位乘法串行输入电流输出数模转换器DAC模块ALTIUM原理图+PCB文件,硬件4层板设计,大小为66mmx39mm,ALTIUM设计的工程文件,包括完整的原理图和PCB文件,可以做为你的设计参考。 原理图器件列表: Library Component Count : 14 Name                Description ---------------------------------------------------------------------------------------------------- AD8397ARDZ          Imported Capacitor           CAP.,1uF,X74,10V,10%,1206 Header 10X1 2.54 Header, 100mil, 2x1_1Header, 100mil, 2x1, Tin plated, TH Header, 100mil, 3x1 Header, 100mil, 3x1, Tin plated, TH KJDZ-2              快接端子 LT1012              LT1012 LT1360              LT1360 LTC2054_1           LTC2054 LTC2756AIG          LTC2756AIG LTC6244             Imported LTC6655             LTC6655 Resistor            RES.,1K OHMS,5%,1/16W,0603 SMA-KE              CONNECTOR, SHEILDED, END LAUNCH JACK, GOLD PLATED, FOR 0.062 PCB, EDGE MOUNTED

    标签: 数模转换器

    上传时间: 2021-12-22

    上传用户:

  • PW2606B.pdf规格书下载

    The PW2606B is a front-end over voltage and over current protection device. It achieves wide inputvoltage range from 2.5VDC to 40VDC. The over voltage threshold can be programmed externally orset to internal default setting. The low resistance of integrated power path nFET switch ensures betterperformance for battery charging system applications. It can deliver up to 1A current to satisfy thebattery supply system. It integrates the over-temperature protection shutdown and auto-recoverycircuit with hysteresis to protect against over current events

    标签: pw2606b

    上传时间: 2022-02-11

    上传用户:

  • PW2601_2.0.pdf规格书下载

    The PW2601 is a charger front-end integrated circuit designed to provide protection to Li-ionbatteries from failures of charging circuitry. The device monitors the input voltage, battery voltageand the charging current to make sure all three parameters are operated in normal range. Thedevice will switch off internal MOSFET to disconnect IN to OUT to protect load when any of inputvoltage, output current exceeds the threshold. The Over temperature protection (OTP) functionmonitors chip temperature to protect the device. The PW2601 also can protect the system’sbattery from being over charged by monitors the battery voltage continuously. The deviceoperates like a linear regulator, maintaining a 5.1V output with input voltages up to the input overvoltage threshold.The PW2601 is available in DFN-2x2-8L package. Standard products are Pb-free and Halogenfree

    标签: pw2601

    上传时间: 2022-02-11

    上传用户: