The first task at hand is to set up the endpoints appropriately for this example. The following code switches the CPU Clock speed to 48 MHz (since at power-on default it is 12 MHz), and sets up EP2 as a Bulk OUT endpoint, 4x buffered of size 512, and EP6 as a Bulk IN endpoint, also 4x buffered of size 512. This set-up utilizes the maximum allotted 4-KB FIFO space. It also sets up the FIFOs for manual mode, word-wide operation, and goes through a FIFO reset and arming sequence to ensure that they are ready for data operations
标签： appropriately The endpoints following
上传时间： 2013-12-02
上传用户：dianxin61
在主机上编译后，上传Clock，重起开发板。 在主机上编译后，上传Clock，重起开发板。
上传时间： 2014-11-26
上传用户：xaijhqx
在主机上编译后，上传INT，重起开发板。 在主机上编译后，上传Clock，重起开发板。
上传时间： 2016-03-20
上传用户：sammi
小而全的软盘镜像文件，原创！fbdisk-坏道屏蔽；Clock-时钟显示；支持DOS下USB，快速分区；杀进程killer.exe gdisk-最好的分区工具，方法见fd.txt。
上传时间： 2013-12-13
上传用户：playboys0
This example describes how to use the ADC and DMA to transfer continuously converted data from ADC to a data buffer. The ADC is configured to converts continuously ADC channel14. Each time an end of conversion occurs the DMA transfers, in circular mode, the converted data from ADC1 DR register to the ADC_ConvertedValue variable. The ADC1 Clock is set to 14 MHz.
标签： continuously ADC describes converted
上传时间： 2014-01-03
上传用户：徐孺
NRF905驱动代码 // The content of this struct is nRF905 s initialize data. // CH_NO=1 433MHZ Normal Opration,No Retrans RX,TX Address is 4 Bytes // RX TX Payload Width is 32 Bytes Disable Extern Clock Fosc=16MHZ // 8 Bits CRC And enable
标签： initialize 905 content Normal
上传时间： 2013-12-16
上传用户：lanjisu111
vhdl编写，8b—10b 编解码器设计 Encoder: 8b/10b Encoder (file: 8b10b_enc.vhd) Synchronous Clocked inputs (latched on each Clock rising edge) 8-bit parallel unencoded data input KI input selects data or control encoding Asynchronous active high reset initializes all logic Encoded data output 10-bit parallel encoded output valid 1 Clock later Decoder: 8b/10b Decoder (file: 8b10b_dec.vhd) Synchronous Clocked inputs (latched on each Clock rising edge) 10-bit parallel encoded data input Asynchronous active high reset initializes all logic Decoded data, disparity and KO outputs 8-bit parallel unencoded output valid 1 Clock later
上传时间： 2016-05-05
上传用户：gundamwzc
16位cpu设计VHDL源码，其中包括alu，Clock，memory等部分的设计
上传时间： 2016-06-30
上传用户：saharawalker
This assignment requires you to complete the dynamic drawing components of the Date/Time Control Panel from the previous two programming assignments. In particular, you will be moving the map found in the "Time Zone" tab when the time zone changes and will be drawing a Clock face corresponding to the time setting.
标签： assignment components the requires
上传时间： 2016-07-03
上传用户：JIUSHICHEN
s3c2410平台的开发详解 包括 开发环境 linux的 还有 gdb的 还有基础实验 包括LED I/O, linux, memory , flash , uart , 中断,timer ,mmu, Clock还有bootloader vivi等 初学者的 宝典 强烈推荐
标签： linux s3c2410 memory flash
上传时间： 2014-01-25
上传用户：wangyi39
