s3c2410 ads下的测试程序移植到 iar ewarm v5.2；包括 Please select function : 0 : Please input 1-14 to select test 1 : Real time Clock display 2 : 4 key array test 3 : Buzzer test 4 : ADC test 5 : IIC EEPROM test 6 : Touchpanel test 7 : 3.5# TFT LCD 240*320 test 8 : UDA1341 play audio test 9 : UDA1341 record audio test 10 : IRDA test 11 : SD Card write and read test 12 : COM port ( UART2 ) test
标签： Please select function s3c2410
上传时间： 2016-10-01
上传用户：225588
The Inter IC bus or I2C bus is a simple bidirectional two wire bus designed primarily for general control and data transfer communication between ICs. Some of the features of the I2C bus are: • Two signal lines, a serial data line (SDA) and a serial Clock line (SCL), and ground are required. A 12V supply line (500mA max.) for powering the peripherals often may be present. • Each device connected to the bus is software addressable by a unique address and simple master/ slave relationships exist at all times masters can operate as master-transmitters or as master-receivers. • The I2C bus is a true multi-master bus including collision detection and arbitration to prevent data corruption if two or more masters simultaneously initiate data transfer systems. • Serial, 8-bit oriented, bidirectional data transfers can be made at up to 100 KBit/s in the standard mode or up to 400 KBit/s in the fast mode.
标签： bus bidirectional primarily designed
上传时间： 2013-12-11
上传用户：jeffery
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at Clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上传时间： 2013-12-13
上传用户：himbly
Top module name : SHIFTER (File name : SHIFTER.v) 2. Input pins: SHIFT [3:0], IN [15:0], SIGN, RIGHT. 3. Output pins: OUT [15:0]. 4. Input signals generated from test pattern are latched in one cycle and are synchronized at Clock rising edge. 5. The SHIFT signal describes the shift number. The shift range is 0 to 15. 6. When the signal RIGHT is high, it shifts input data to right. On the other hand, it shifts input data to left. 7. When the signal SIGN is high, the input data is a signed number and it shifts with sign extension. However, the input data is an unsigned number if the signal SIGN is low. 8. You can only use following gates in Table I and need to include the delay information (Tplh, Tphl) in your design.
上传时间： 2014-01-20
上传用户：三人用菜
大学计算机操作系统课程设计，完成页面置换功能，利用Clock算法
上传时间： 2014-02-01
上传用户：杜莹12345
本模拟I2C软件包包含了I2C操作的底层子程序，使用前要定义 好SCL和SDA。在标准8051模式(12 Clock)下,对主频要求是不高于12MHz(即1个 机器周期1us) 若Fosc>12MHz则要增加相应的NOP指令数。(总线时序符合I2C标 准模式,100Kbit/S)。
上传时间： 2013-12-08
上传用户：ruixue198909
The XC226x derivatives are high-performance members of the Infineon XC2000 Family of full-feature single-chip CMOS microcontrollers. These devices extend the functionality and performance of the C166 Family in terms of instructions (MAC unit), peripherals, and speed. They combine high CPU performance (up to 80 million instructions per second) with extended peripheral functionality and enhanced IO capabilities. Optimized peripherals can be adapted flexibly to meet the application requirements. These derivatives utilize Clock generation via PLL and internal or external Clock sources. Onchip memory modules include program Flash, program RAM, and data RAM.
标签： high-performance full-feature derivatives Infineon
上传时间： 2016-12-12
上传用户：wab1981
DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a Clock rate of 133 MHz, 16-bit data changes at both Clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上传时间： 2014-11-01
上传用户：l254587896
利用QuartusII的"MegaWizard Plug-In Manager", 设计输入数据宽度是4bit的ADD、SUB、MULT、DIVIDE、COMPARE 把它们作为一个project,DEVICE选用EPF10K70RC240-4，对它们进行 时序仿真，将仿真波形（输入输出选用group）在一页纸上打印出来。 2.利用QuartusII的"MegaWizard Plug-In Manager"中的LPM_COUNTER， 设计一个20bit的up_only COUNTER, 要求该COUNTER在FE0FA和FFFFF之间自动循环计数； 分析该COUNTER在EPM7128SLC84-7、EPM7128SLC84-10、和EPF10K70RC240-2、 EPF10K70RC240-4几种芯片中的最大工作频率； 请将计数器的输出值在FFFFC--FE0FF之间的仿真波形打印出来 （仅EPF10K70RC240-4芯片,最大允许Clock频率下）。
标签： MegaWizard QuartusII Manager COMPARE
上传时间： 2016-12-26
上传用户：王者A
595——8位数码管循环移位显示.doc │ 利用74HC595实现多位LED显示的新方法.doc │ 用74HC595芯片驱动LED的电路设计.pdf │ 文件目录表绘制.cmd │ 文件夹目录.txt │ 文件名目录.txt │ ├─点阵设计 │ 74HC595PW.pdf │ 正文点阵设计.doc │ ├─Use595_4(Alexi) │ Use595_2.c │ Use595_4.hex │ Use595_4(Alexi).PWI │ Use595_4(Alexi).DSN │ ├─电子钟（595） │ EClock_2.hex │ EClock_2.c │ EClock_2.Opt │ EClock_2.Uv2 │ EClock_2_1.hex │ E-Clock.DSN │ E-Clock.PWI │ └─资料介绍 595.jpg 74HC595真值表.png 74hc595.doc ★595引脚介绍★.doc 74HC595PW.pdf
上传时间： 2014-01-07
上传用户：aa17807091
