The MIPS32® 4KEm™ core from MIPS® Technologies is a member of the MIPS32 4KE™ processor core family. It is a high-performance, low-power, 32-bit MIPS RISC core designed for custom system-on-silicon applications. The core is designed for semiconductor manufacturing companies, ASIC developers, and system OEMs who want to rapidly integrate their own custom logic and peripherals with a high-performance RISC processor. It is highly portable across processes, and can be easily integrated into full system-on-silicon designs, allowing developers to focus their attention on end-user products. The 4KEm core is ideally positioned to support new products for emerging segments of the digital consumer, network, systems, and information management markets, enabling new tailored solutions for embedded applications.
标签： MIPS 8482 Technologies 174
上传时间： 2014-12-22
上传用户：semi1981
VHDL语言实现的穿行通讯，可实现闭环操作，通讯过程中每个bit位采样3次，保证数据准确。
上传时间： 2014-01-13
上传用户：ynsnjs
DDR SDRAM控制器的VHDL源代码，含详细设计文档。 The DDR, DCM, and SelectI/O™ features in the Virtex™ -II architecture make it the perfect choice for implementing a controller of a Double Data Rate (DDR) SDRAM. The Digital Clock Manager (DCM) provides the required Delay Locked Loop (DLL), Digital Phase Shift (DPS), and Digital Frequency Synthesis (DFS) functions. This application note describes a controller design for a 16-bit DDR SDRAM. The application note and reference design are enhanced versions of XAPP200 targeted to the Virtex-II series of FPGAs. At a clock rate of 133 MHz, 16-bit data changes at both clock edges. The reference design is fully synthesizable and achieves 133 MHz performance with automatic place and route tools.
上传时间： 2014-11-01
上传用户：l254587896
软件简介：HI-TECH PICC 是一款高效的C编译器，支持Microchip PICmicro 10/12/14/16/17系列控制器。是一款强劲的标准C编译器，完全遵守ISO/ANSI C，支持所有的数据类型包括24 and 32 bit IEEE 标准浮点类型。智能优化产生高质量的代码。属于第三方开发工具。能和MPLAB整合，内嵌开发环境（HI－TIDE）。 Hi-tech PICC Compiler v8.注册码 Serial: HCPIC-88888 First Name: ONE Last Name: TWO Company Name:ONE TWO Registration: 任意填，但一定要填 Activation: NPCBACMJKLPCADKLOEDBFPIOCIBAEIDI
上传时间： 2016-12-16
上传用户：Andy123456
H.264/AVC, the result of the collaboration between the ISO/IEC Moving Picture Experts Group and the ITU-T Video Coding Experts Group, is the latest standard for video coding. The goals of this standardization effort were enhanced compression efficiency, network friendly video representation for interactive (video telephony) and non-interactive applications (broadcast, streaming, storage, video on demand). H.264/AVC provides gains in compression efficiency of up to 50％ over a wide range of bit rates and video resolutions compared to previous standards. Compared to previous standards, the decoder complexity is about four times that of MPEG-2 and two times that of MPEG-4 Visual Simple Profile. This paper provides an overview of the new tools, features and complexity of H.264/AVC.
标签： the collaboration between Experts
上传时间： 2013-12-30
上传用户：dongbaobao
*** *** *** *** *** *** ***** ** Two wire/I2C Bus READ/WRITE Sample Routines of Microchip s ** 24Cxx / 85Cxx serial CMOS EEPROM interfacing to a ** PIC16C54 8-bit CMOS single chip microcomputer ** Revsied Version 2.0 (4/2/92). ** ** Part use = PIC16C54-XT/JW ** Note: 1) All timings are based on a reference crystal frequency of 2MHz ** which is equivalent to an instruction cycle time of 2 usec. ** 2) Address and literal values are read in octal unless otherwise ** specified.
标签： Microchip Routines Sample WRITE
上传时间： 2013-12-27
上传用户：ljmwh2000
selects the mux channel and configures the MAX197 for second write pulse, written with ACQMOD = 0, termi- either unipolar or bipolar input range. A write pulse (WR nates acquisition and starts conversion on WR°Os risin + CS) can either start an acquisition interval or initiate a edge (Figure 6). However, if the second control byte combined acquisition plus conversion. The sampling contains ACQMOD = 1, an indefinite acquisition interval interval occurs at the end of the acquisition interval. is restarted. The ACQMOD bit in the input control byte offer
标签： configures the selects channel
上传时间： 2013-12-09
上传用户：
selects the mux channel and configures the MAX197 for second write pulse, written with ACQMOD = 0, termi- either unipolar or bipolar input range. A write pulse (WR nates acquisition and starts conversion on WR°Os risin + CS) can either start an acquisition interval or initiate a edge (Figure 6). However, if the second control byte combined acquisition plus conversion. The sampling contains ACQMOD = 1, an indefinite acquisition interval interval occurs at the end of the acquisition interval. is restarted. The ACQMOD bit in the input control byte offer
标签： configures the selects channel
上传时间： 2016-12-24
上传用户：朗朗乾坤
selects the mux channel and configures the MAX197 for second write pulse, written with ACQMOD = 0, termi- either unipolar or bipolar input range. A write pulse (WR nates acquisition and starts conversion on WR°Os risin is restarted. The ACQMOD bit in the input control byte offer+ CS) can either start an acquisition interval or initiate a edge (Figure 6). However, if the second control byte combined acquisition plus conversion. The sampling contains ACQMOD = 1, an indefinite acquisition interval interval occurs at the end of the acquisition interval.
标签： configures the selects channel
上传时间： 2016-12-24
上传用户：yzhl1988
MAX1142是一款高性能的模入芯片，采集范围14-bit，支持SPI接口。 提供内部时钟和外部时钟采集方式。
上传时间： 2016-12-31
上传用户：1101055045
