由lnfineon Technologies (IT)公司推出的COOLMOS ICE2A165／2,65／365系列芯片是PWM+MOSFET二合一芯片，其优点是：用它做开关电源，无需加散热器，在通用电网即可输出20～50W 的功率；保护功能齐全；电路结构简单；能自动降低空载时的工作频率，从而降低待机状态的损耗，故在中小功率开关电源中有着广泛的应用前景。
上传时间： 2013-11-09
上传用户：chenjjer
利用负阻原理设计了5.9 GHz介质振荡器（DRO），采用HFSS软件对介质谐振块（DR）进行三维仿真，应用Agilent公司的ADS软件对DRO进行了优化设计和非线性分析，用该方法制作的并联反馈式DRO性能良好，输出功率为10 dBm，相位噪声达到-100 dBc/Hz＠10 kHz，-124 dBc/Hz＠100 kHz。
上传时间： 2013-10-10
上传用户：urgdil
This application note is an overview discussion of theLinear Technology SPICE macromodel library. It assumeslittle if any prior knowledge of this software library or itshistory. However, it does assume familiarity with both theanalog simulation program SPICE (or one of its manyderivatives), and modern day op amps, including bipolar,JFET, and MOSFET amplifier technologies
上传时间： 2013-11-14
上传用户：zhanditian
COOLMOS ICE2A165/265/365是Infineon technologies 公司推出的系列PWM+MOSFET二合一芯片，其突出特点是由其组成的开关电源，在市电电网中工作时，无需外加散热器即可输出20～50W的输出功率;且能自动降低空载时的工作频率，从而降低待机状态的损耗;同时还具有过、欠压保护、过热保护、过流保护以及自恢复功能，因而在中小功率开关电源中有着广泛 的应用前景
上传时间： 2013-10-17
上传用户：HGH77P99
以C8051F020为核心处理器，设计无线传感器网络数据采集系统。系统采用SZ05-ADV型无线通讯模块组建Zigbee无线网络，结合嵌入式系统的软硬件技术，完成终端节点的8路传感器信号的数据采集。现场8路信号通过前端处理后，分别送入C8051F020的12位A/D转换器进行转换。经过精确处理、存储后的现场数据，通过Zigbee无线网络传送到上位机，系统可达到汽车试验中无线测试的目的。 Abstract: This paper designs a wireless sensor network system for data acquisition with C8051F020 as core processors.The system used SZ05-ADV wireless communication module，set up a Zigbee wireless network， combined with hardware and software technologies of embedded systems，completed the end-node 8-locale sensor signal data acquisition.Eight locale signals were sent separately into the 12-bit ADC of C8051F020 for conversion through front treatment.After accurate processing and storage，the locale data was transmitted to the host computer through Zigbee wireless.The system achieves the purpose of wireless testing in vehicle trial.
标签： C8051F020 Zigbee 汽车测试 系统设计
上传时间： 2013-11-23
上传用户：dsgkjgkjg
IntroductionAs chip designers pack more functions into ICs,pin counts continue to grow and the space betweenpins keeps shrinking. Pin spacings of 0.5 mm and0.65 mm are not at all uncommon. The power ofthese new ICs is wonderful, to be sure, but trou-bleshooting them can be a chore because connect-ing scopes and logic analyzers has become muchmore difficult and less dependable.
标签： Agilent Probing Wedge High
上传时间： 2013-10-22
上传用户：蒋清华嗯
Virtex-5, Spartan-DSP FPGAs Application Note This application note demonstrates how efficient implementations of Digital Up Converters(DUC) and Digital Down Converters (DDC) can be done by leveraging the Xilinx DSP IPportfolio for increased productivity and reduced time to development. Step-by-step instruction is given on how to perform system-level trade off analysis and develop the most efficient FPGA implementation, thus allowing engineers a flexible, low-cost and low-power alternative to ASSP technologies.
标签： Spartan-DSP Virtex FPGAs Ap
上传时间： 2013-10-23
上传用户：raron1989
中文版详情浏览：http://www.elecfans.com/emb/fpga/20130715324029.html Xilinx UltraScale:The Next-Generation Architecture for Your Next-Generation Architecture The Xilinx® UltraScale™ architecture delivers unprecedented levels of integration and capability with ASIC-class system- level performance for the most demanding applications. The UltraScale architecture is the industr y's f irst application of leading-edge ASIC architectural enhancements in an All Programmable architecture that scales from 20 nm planar through 16 nm FinFET technologies and beyond, in addition to scaling from monolithic through 3D ICs. Through analytical co-optimization with the X ilinx V ivado® Design Suite, the UltraScale architecture provides massive routing capacity while intelligently resolving typical bottlenecks in ways never before possible. This design synergy achieves greater than 90% utilization with no performance degradation. Some of the UltraScale architecture breakthroughs include: • Strategic placement (virtually anywhere on the die) of ASIC-like system clocks, reducing clock skew by up to 50% • Latency-producing pipelining is virtually unnecessary in systems with massively parallel bus architecture, increasing system speed and capability • Potential timing-closure problems and interconnect bottlenecks are eliminated, even in systems requiring 90% or more resource utilization • 3D IC integration makes it possible to build larger devices one process generation ahead of the current industr y standard • Greatly increased system performance, including multi-gigabit serial transceivers, I/O, and memor y bandwidth is available within even smaller system power budgets • Greatly enhanced DSP and packet handling The Xilinx UltraScale architecture opens up whole new dimensions for designers of ultra-high-capacity solutions.
标签： UltraScale Xilinx 架构
上传时间： 2013-11-13
上传用户：瓦力瓦力hong
Introduction to Xilinx Packaging Electronic packages are interconnectable housings for semiconductor devices. The major functions of the electronic packages are to provide electrical interconnections between the IC and the board and to efficiently remove heat generated by the device. Feature sizes are constantly shrinking, resulting in increased number of transistors being packed into the device. Today's submicron technology is also enabling large-scale functional integration and system-on-a-chip solutions. In order to keep pace with these new advancements in silicon technologies, semiconductor packages have also evolved to provide improved device functionality and performance. Feature size at the device level is driving package feature sizes down to the design rules of the early transistors. To meet these demands, electronic packages must be flexible to address high pin counts, reduced pitch and form factor requirements. At the same time,packages must be reliable and cost effective.
上传时间： 2013-10-22
上传用户：ztj182002
目录•FPGA调试的挑战•传统的FPGA调试方案•Agilent FPGA动态探头的调试方案•总结
上传时间： 2013-10-31
上传用户：cccole0605
