代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/468753/6987494
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity mux24 is
port(
i0 : in vl_logic_vector(3 downto 0);
i1 : in vl_logic_vector(3 downto 0);
www.eeworm.com/read/468753/6987503
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity sum4 is
port(
s : out vl_logic_vector(3 downto 0);
p : in vl_logic_vector(3 downto 0);
www.eeworm.com/read/468104/6999963
rpt test.map.rpt
Analysis & Synthesis report for test
Wed Apr 22 21:04:05 2009
Quartus II Version 8.1 Build 163 10/28/2008 SJ Full Version
---------------------
; Table of Contents ;
---------------------
www.eeworm.com/read/467084/7015430
qmsg crc.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0}
{ "I
www.eeworm.com/read/465636/7050912
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity spi_slave_model is
generic(
tp : integer := 1
);
port(
rst : in vl_logic;
ss
www.eeworm.com/read/465358/7053680
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity glbl is
generic(
roc_width : integer := 100000;
toc_width : integer := 0
);
end glbl;
www.eeworm.com/read/465358/7053727
prj i2c_master_top.prj
verilog work i2c_master_bit_ctrl.v
verilog work i2c_master_byte_ctrl.v
verilog work i2c_master_top.v
www.eeworm.com/read/465033/7064434
hif shifter.hif
Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
38
2277
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Sta
www.eeworm.com/read/433541/7103119
hif aaa3_8.hif
Version 7.2 Build 151 09/26/2007 SJ Full Version
11
1009
OFF
OFF
OFF
OFF
ON
ON
ON
FV_OFF
Level2
0
0
VRSM_ON
VHSM_ON
0
-- Start Partition --
-- End Partition --
-- Start Library Path
www.eeworm.com/read/264839/7110819
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity mux_x is
port(
i : in vl_logic_vector(2 downto 0);
x_i : out vl_logic_vector(7 downto 0);