_primary.vhd

来自「ARM10 INSTALALTION GUIDE」· VHDL 代码 · 共 10 行

library verilog;
use verilog.vl_types.all;
entity sum4 is
    port(
        s               : out    vl_logic_vector(3 downto 0);
        p               : in     vl_logic_vector(3 downto 0);
        c               : in     vl_logic_vector(3 downto 0)
    );
end sum4;