_primary.vhd

来自「fpga功能实现有限字长响应FIR 用verilog编写」· VHDL 代码 · 共 26 行

library verilog;
use verilog.vl_types.all;
entity mux_x is
    port(
        i               : in     vl_logic_vector(2 downto 0);
        x_i             : out    vl_logic_vector(7 downto 0);
        x_Ni            : out    vl_logic_vector(7 downto 0);
        x0              : in     vl_logic_vector(7 downto 0);
        x1              : in     vl_logic_vector(7 downto 0);
        x2              : in     vl_logic_vector(7 downto 0);
        x3              : in     vl_logic_vector(7 downto 0);
        x4              : in     vl_logic_vector(7 downto 0);
        x5              : in     vl_logic_vector(7 downto 0);
        x6              : in     vl_logic_vector(7 downto 0);
        x7              : in     vl_logic_vector(7 downto 0);
        x8              : in     vl_logic_vector(7 downto 0);
        x9              : in     vl_logic_vector(7 downto 0);
        x10             : in     vl_logic_vector(7 downto 0);
        x11             : in     vl_logic_vector(7 downto 0);
        x12             : in     vl_logic_vector(7 downto 0);
        x13             : in     vl_logic_vector(7 downto 0);
        x14             : in     vl_logic_vector(7 downto 0);
        x15             : in     vl_logic_vector(7 downto 0)
    );
end mux_x;