_primary.vhd

来自「SPI 总线协议源码SPI 总线协议源码SPI 总线协议源码」· VHDL 代码 · 共 15 行

library verilog;
use verilog.vl_types.all;
entity spi_slave_model is
    generic(
        tp              : integer := 1
    );
    port(
        rst             : in     vl_logic;
        ss              : in     vl_logic;
        sclk            : in     vl_logic;
        mosi            : in     vl_logic;
        miso            : out    vl_logic
    );
end spi_slave_model;