crc.map.qmsg

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{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu Mar 22 14:49:08 2007 " "Info: Processing started: Thu Mar 22 14:49:08 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off CRC -c CRC " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off CRC -c CRC" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "CRC.vhd 2 1 " "Info: Found 2 design units, including 1 entities, in source file CRC.vhd" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 CRC-behav " "Info: Found design unit 1: CRC-behav" {  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 16 -1 0 } }  } 0 0 "Found design unit %1!d!: %2!s!" 0 0} { "Info" "ISGN_ENTITY_NAME" "1 CRC " "Info: Found entity 1: CRC" {  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 7 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0}  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "CRC " "Info: Elaborating entity \"CRC\" for the top level hierarchy" {  } {  } 0 0 "Elaborating entity \"%1!s!\" for the top level hierarchy" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "data_CRC CRC.vhd(19) " "Warning (10631): VHDL Process Statement warning at CRC.vhd(19): inferring latch(es) for signal or variable \"data_CRC\", which holds its previous value in one or more paths through the process" {  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Warning" "WVRFX_VHDL_ID_IN_COMB_PROCESS_HOLDS_VALUE" "s CRC.vhd(19) " "Warning (10631): VHDL Process Statement warning at CRC.vhd(19): inferring latch(es) for signal or variable \"s\", which holds its previous value in one or more paths through the process" {  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 0 0 } }  } 0 10631 "VHDL Process Statement warning at %2!s!: inferring latch(es) for signal or variable \"%1!s!\", which holds its previous value in one or more paths through the process" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "s\[0\] CRC.vhd(19) " "Info (10041): Verilog HDL or VHDL info at CRC.vhd(19): inferred latch for \"s\[0\]\"" {  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "s\[1\] CRC.vhd(19) " "Info (10041): Verilog HDL or VHDL info at CRC.vhd(19): inferred latch for \"s\[1\]\"" {  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "s\[2\] CRC.vhd(19) " "Info (10041): Verilog HDL or VHDL info at CRC.vhd(19): inferred latch for \"s\[2\]\"" {  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "data_CRC\[0\] CRC.vhd(19) " "Info (10041): Verilog HDL or VHDL info at CRC.vhd(19): inferred latch for \"data_CRC\[0\]\"" {  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "data_CRC\[1\] CRC.vhd(19) " "Info (10041): Verilog HDL or VHDL info at CRC.vhd(19): inferred latch for \"data_CRC\[1\]\"" {  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "data_CRC\[2\] CRC.vhd(19) " "Info (10041): Verilog HDL or VHDL info at CRC.vhd(19): inferred latch for \"data_CRC\[2\]\"" {  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "data_CRC\[3\] CRC.vhd(19) " "Info (10041): Verilog HDL or VHDL info at CRC.vhd(19): inferred latch for \"data_CRC\[3\]\"" {  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "data_CRC\[4\] CRC.vhd(19) " "Info (10041): Verilog HDL or VHDL info at CRC.vhd(19): inferred latch for \"data_CRC\[4\]\"" {  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "data_CRC\[5\] CRC.vhd(19) " "Info (10041): Verilog HDL or VHDL info at CRC.vhd(19): inferred latch for \"data_CRC\[5\]\"" {  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "IVRFX_VRFC_LATCH_INFERRED" "data_CRC\[6\] CRC.vhd(19) " "Info (10041): Verilog HDL or VHDL info at CRC.vhd(19): inferred latch for \"data_CRC\[6\]\"" {  } { { "CRC.vhd" "" { Text "D:/WORKSPACE (K)/TEC-CA/教师用光盘/第6章实验/实验6.2——编码实验：CRC码/CRC.vhd" 19 0 0 } }  } 0 10041 "Verilog HDL or VHDL info at %2!s!: inferred latch for \"%1!s!\"" 0 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "38 " "Info: Implemented 38 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "12 " "Info: Implemented 12 input pins" {  } {  } 0 0 "Implemented %1!d! input pins" 0 0} { "Info" "ISCL_SCL_TM_OPINS" "10 " "Info: Implemented 10 output pins" {  } {  } 0 0 "Implemented %1!d! output pins" 0 0} { "Info" "ISCL_SCL_TM_LCELLS" "16 " "Info: Implemented 16 logic cells" {  } {  } 0 0 "Implemented %1!d! logic cells" 0 0}  } {  } 0 0 "Implemented %1!d! device resources after synthesis - the final resource count might be different" 0 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu Mar 22 14:49:11 2007 " "Info: Processing ended: Thu Mar 22 14:49:11 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:03 " "Info: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was successful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}