代码搜索：verilog hdl 是什么？
找到约 10,000 项符合「verilog hdl 是什么？」的源代码
代码结果 10,000
www.eeworm.com/read/347114/11693972
_info
m255
cModel Technology
dD:\quartus_30\quartus\tpi\mgc_oem
vAND1
I5QbEGUY4LPF__LOC09K
www.eeworm.com/read/347114/11699277
_info
m255
cModel Technology
dD:\quartus_30\quartus\tpi\mgc_oem
vand1
VzNO3AF7X_1hjETK^b?5423
r1
31
OE;L;5.6;17
IbX`i3
d.
FQuartusIIVersion3.0($MODEL_TECH/../altera/Verilog/src/stratixgx_at
www.eeworm.com/read/347114/11699527
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity and16 is
port(
\Y\ : out vl_logic_vector(15 downto 0);
\IN1\ : in vl_logic_vector(15 downto 0)
);
www.eeworm.com/read/347114/11699564
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity pll_reg is
port(
q : out vl_logic;
clk : in vl_logic;
ena : in vl_logic;
www.eeworm.com/read/156808/11762807
qmsg xiaolizi1588.map.qmsg
{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info:
www.eeworm.com/read/156456/11802485
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity divf_divf_test_v_tf is
end divf_divf_test_v_tf;
www.eeworm.com/read/345513/11810676
vif match_rec.vif
#
# Synplicity Verification Interface File
# Generated using Synplify-pro
#
# Copyright (c) 1996-2005 Synplicity, Inc.
# All rights reserved
#
# Set logfile options
vif_set_result_file matc
www.eeworm.com/read/155194/11889884
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity decQPSK is
port(
clk : in vl_logic;
reset : in vl_logic;
bita : in vl_logic;
www.eeworm.com/read/155192/11890014
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity frame is
generic(
CAP : integer := 0;
SUS : integer := 1
);
port(
clk : in
www.eeworm.com/read/153541/12028847
vhd _primary.vhd
library verilog;
use verilog.vl_types.all;
entity comp1 is
port(
o : out vl_logic;
s : out vl_logic;
a : in vl_logic;