代码搜索:verilog hdl 是什么?

找到约 10,000 项符合「verilog hdl 是什么?」的源代码

代码结果 10,000
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smsg mips_top.map.smsg

Warning (10268): Verilog HDL information at clock_gen.v(13): Always Construct contains both blocking and non-blocking assignments Warning (10268): Verilog HDL information at Ifetch32.v(29): Always Co
www.eeworm.com/read/299076/7890015

smsg vga.map.smsg

Info (10281): Verilog HDL Declaration information at vga_tgen.v(41): object "vgate" differs only in case from object "Vgate" in the same scope Warning (10236): Verilog HDL Implicit Net warning at vga
www.eeworm.com/read/244601/12853127

smsg freq.map.smsg

Warning (10268): Verilog HDL information at Control.v(66): Always Construct contains both blocking and non-blocking assignments Warning (10273): Verilog HDL warning at Display.v(20): extended using "
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qmsg alu.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0} { "I
www.eeworm.com/read/305111/13778604

smsg ps2rs232.map.smsg

Warning (10273): Verilog HDL warning at rcvr.v(50): extended using "x" or "z" Warning (10268): Verilog HDL information at rcvr.v(97): Always Construct contains both blocking and non-blocking assignme
www.eeworm.com/read/490774/6442290

qmsg prev_cmp_adc.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 0
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qmsg prev_cmp_adc.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 0
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smsg adc.map.smsg

Warning (10273): Verilog HDL warning at ADC.v(132): extended using "x" or "z" Warning (10268): Verilog HDL information at ADC.v(66): always construct contains both blocking and non-blocking assignmen
www.eeworm.com/read/488475/6487587

smsg part4.map.smsg

Warning (10273): Verilog HDL warning at part4.v(22): extended using "x" or "z" Warning (10268): Verilog HDL information at part4.v(32): always construct contains both blocking and non-blocking assign
www.eeworm.com/read/488254/6499568

qmsg prev_cmp_half_clk.map.qmsg

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" { } { } 3 0 "*******************************************************************" 0 0 "" 0 0