prev_cmp_half_clk.map.qmsg

verilog hdl经典例程

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version " "Info: Version 8.0 Build 231 07/10/2008 Service Pack 1 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sat May 16 10:39:30 2009 " "Info: Processing started: Sat May 16 10:39:30 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off half_clk -c half_clk " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off half_clk -c half_clk" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WVRFX_L2_VERI_ID_IS_SV_KEYWORD" "int half_clk.v(2) " "Warning (10463): Verilog HDL Declaration warning at half_clk.v(2): \"int\" is SystemVerilog-2005 keyword" {  } { { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 2 0 0 } }  } 0 10463 "Verilog HDL Declaration warning at %2!s!: \"%1!s!\" is SystemVerilog-2005 keyword" 0 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "half_clk.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file half_clk.v" { { "Info" "ISGN_ENTITY_NAME" "1 half_clk " "Info: Found entity 1: half_clk" {  } { { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 1 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Error" "EVRFX_VERI_PORT_UNDECLARED" "reset half_clk.v(1) " "Error (10158): Verilog HDL Module Declaration error at half_clk.v(1): port \"reset\" is not declared as port" {  } { { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 1 0 0 } }  } 0 10158 "Verilog HDL Module Declaration error at %2!s!: port \"%1!s!\" is not declared as port" 0 0 "" 0 0}
{ "Error" "EVRFX_VERI_PORT_UNDECLARED" "clk_in half_clk.v(1) " "Error (10158): Verilog HDL Module Declaration error at half_clk.v(1): port \"clk_in\" is not declared as port" {  } { { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 1 0 0 } }  } 0 10158 "Verilog HDL Module Declaration error at %2!s!: port \"%1!s!\" is not declared as port" 0 0 "" 0 0}
{ "Error" "EVRFX_VERI_UNDECLARED_OBJECT" "int half_clk.v(2) " "Error (10161): Verilog HDL error at half_clk.v(2): object \"int\" is not declared" {  } { { "half_clk.v" "" { Text "E:/lab/half_clk/half_clk.v" 2 0 0 } }  } 0 10161 "Verilog HDL error at %2!s!: object \"%1!s!\" is not declared" 0 0 "" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 1  Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 1 warning" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "159 " "Error: Peak virtual memory: 159 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Error" "EQEXE_END_BANNER_TIME" "Sat May 16 10:39:31 2009 " "Error: Processing ended: Sat May 16 10:39:31 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Error: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}