prev_cmp_adc.qmsg

对AD0809进行操作

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 8.0 Build 215 05/29/2008 SJ Full Version " "Info: Version 8.0 Build 215 05/29/2008 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0 "" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun May 24 14:42:01 2009 " "Info: Processing started: Sun May 24 14:42:01 2009" {  } {  } 0 0 "Processing started: %1!s!" 0 0 "" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0 "" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off ADC -c ADC " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off ADC -c ADC" {  } {  } 0 0 "Command: %1!s!" 0 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_XZ_EXTEND_SIGNIFICANT" "ADC.v(132) " "Warning (10273): Verilog HDL warning at ADC.v(132): extended using \"x\" or \"z\"" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 132 0 0 } }  } 0 10273 "Verilog HDL warning at %1!s!: extended using \"x\" or \"z\"" 1 0 "" 0 0}
{ "Warning" "WVRFX_L3_VERI_MIXED_BLOCKING_NONBLOCKING_ASSIGNMENT" "ADC.v(66) " "Warning (10268): Verilog HDL information at ADC.v(66): always construct contains both blocking and non-blocking assignments" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 66 0 0 } }  } 0 10268 "Verilog HDL information at %1!s!: always construct contains both blocking and non-blocking assignments" 1 0 "" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "ADC.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file ADC.v" { { "Info" "ISGN_ENTITY_NAME" "1 ADC " "Info: Found entity 1: ADC" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 13 -1 0 } }  } 0 0 "Found entity %1!d!: %2!s!" 0 0 "" 0 0}  } {  } 0 0 "Found %2!llu! design units, including %3!llu! entities, in source file %1!s!" 0 0 "" 0 0}
{ "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT_TO_NON_REG" "start ADC.v(72) " "Error (10137): Verilog HDL Procedural Assignment error at ADC.v(72): object \"start\" on left-hand side of assignment must have a variable data type" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 72 0 0 } }  } 0 10137 "Verilog HDL Procedural Assignment error at %2!s!: object \"%1!s!\" on left-hand side of assignment must have a variable data type" 0 0 "" 0 0}
{ "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT_TO_NON_REG" "start ADC.v(80) " "Error (10137): Verilog HDL Procedural Assignment error at ADC.v(80): object \"start\" on left-hand side of assignment must have a variable data type" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 80 0 0 } }  } 0 10137 "Verilog HDL Procedural Assignment error at %2!s!: object \"%1!s!\" on left-hand side of assignment must have a variable data type" 0 0 "" 0 0}
{ "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT_TO_NON_REG" "start ADC.v(89) " "Error (10137): Verilog HDL Procedural Assignment error at ADC.v(89): object \"start\" on left-hand side of assignment must have a variable data type" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 89 0 0 } }  } 0 10137 "Verilog HDL Procedural Assignment error at %2!s!: object \"%1!s!\" on left-hand side of assignment must have a variable data type" 0 0 "" 0 0}
{ "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT_TO_NON_REG" "start ADC.v(99) " "Error (10137): Verilog HDL Procedural Assignment error at ADC.v(99): object \"start\" on left-hand side of assignment must have a variable data type" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 99 0 0 } }  } 0 10137 "Verilog HDL Procedural Assignment error at %2!s!: object \"%1!s!\" on left-hand side of assignment must have a variable data type" 0 0 "" 0 0}
{ "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT_TO_NON_REG" "start ADC.v(108) " "Error (10137): Verilog HDL Procedural Assignment error at ADC.v(108): object \"start\" on left-hand side of assignment must have a variable data type" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 108 0 0 } }  } 0 10137 "Verilog HDL Procedural Assignment error at %2!s!: object \"%1!s!\" on left-hand side of assignment must have a variable data type" 0 0 "" 0 0}
{ "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT_TO_NON_REG" "start ADC.v(117) " "Error (10137): Verilog HDL Procedural Assignment error at ADC.v(117): object \"start\" on left-hand side of assignment must have a variable data type" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 117 0 0 } }  } 0 10137 "Verilog HDL Procedural Assignment error at %2!s!: object \"%1!s!\" on left-hand side of assignment must have a variable data type" 0 0 "" 0 0}
{ "Error" "EVRFX_VERI_PROCEDURAL_ASSIGNMENT_TO_NON_REG" "start ADC.v(126) " "Error (10137): Verilog HDL Procedural Assignment error at ADC.v(126): object \"start\" on left-hand side of assignment must have a variable data type" {  } { { "ADC.v" "" { Text "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.v" 126 0 0 } }  } 0 10137 "Verilog HDL Procedural Assignment error at %2!s!: object \"%1!s!\" on left-hand side of assignment must have a variable data type" 0 0 "" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.map.smsg " "Info: Generated suppressed messages file F:/文件存储/设计文件/Quartus II文件/verilog HDL/ADC/ADC.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0 "" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 7 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 7 errors, 0 warnings" { { "Error" "EQEXE_END_PEAK_VSIZE_MEMORY" "154 " "Error: Peak virtual memory: 154 megabytes" {  } {  } 0 0 "Peak virtual memory: %1!s! megabytes" 0 0 "" 0 0} { "Error" "EQEXE_END_BANNER_TIME" "Sun May 24 14:42:04 2009 " "Error: Processing ended: Sun May 24 14:42:04 2009" {  } {  } 0 0 "Processing ended: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:03 " "Error: Elapsed time: 00:00:03" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0 "" 0 0} { "Error" "EQEXE_ELAPSED_CPU_TIME" "00:00:01 " "Error: Total CPU time (on all processors): 00:00:01" {  } {  } 0 0 "Total CPU time (on all processors): %1!s!" 0 0 "" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}
{ "Error" "EFLOW_ERROR_COUNT" "Full Compilation 9 s 0 s " "Error: Quartus II Full Compilation was unsuccessful. 9 errors, 0 warnings" {  } {  } 0 0 "Quartus II %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0 "" 0 0}