alu.map.qmsg

用verilog HDL代码编写的快速除法器

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3 0 "*******************************************************************" 0 0}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 6.0 Build 178 04/27/2006 SJ Full Version " "Info: Version 6.0 Build 178 04/27/2006 SJ Full Version" {  } {  } 0 0 "%1!s!" 0 0} { "Info" "IQEXE_START_BANNER_TIME" "Sun Jul 08 23:19:09 2007 " "Info: Processing started: Sun Jul 08 23:19:09 2007" {  } {  } 0 0 "Processing started: %1!s!" 0 0}  } {  } 4 0 "Running %2!s! %1!s!" 0 0}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off alu -c alu " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off alu -c alu" {  } {  } 0 0 "Command: %1!s!" 0 0}
{ "Error" "EVRFX_VERI_SYNTAX_ERROR" "\"(\";  expecting \";\", or \",\" alu.v(107) " "Error (10170): Verilog HDL syntax error at alu.v(107) near text \"(\";  expecting \";\", or \",\"" {  } { { "alu.v" "" { Text "F:/xf/alu-div/alu.v" 107 0 0 } }  } 0 10170 "Verilog HDL syntax error at %2!s! near text %1!s!" 0 0}
{ "Error" "EVRFX_GENERIC_ERROR_WITH_LOC" "declarations are illegal inside an unnamed block alu.v(107) " "Error (10001): Verilog HDL or VHDL error at alu.v(107): declarations are illegal inside an unnamed block" {  } { { "alu.v" "" { Text "F:/xf/alu-div/alu.v" 107 0 0 } }  } 0 10001 "Verilog HDL or VHDL error at %2!s!: %1!s!" 0 0}
{ "Info" "IVRFX_VERI_OBJ_DIFF_ONLY_IN_CASE" "DIV div alu.v(94) " "Info (10281): Verilog HDL Declaration information at alu.v(94): object \"DIV\" differs only in case from object \"div\" in the same scope" {  } { { "alu.v" "" { Text "F:/xf/alu-div/alu.v" 94 0 0 } }  } 0 10281 "Verilog HDL Declaration information at %3!s!: object \"%1!s!\" differs only in case from object \"%2!s!\" in the same scope" 1 0}
{ "Info" "IVRFX_VERI_OBJ_DECL_HERE" "div alu.v(107) " "Info (10151): Verilog HDL Declaration information at alu.v(107): \"div\" is declared here" {  } { { "alu.v" "" { Text "F:/xf/alu-div/alu.v" 107 0 0 } }  } 0 10151 "Verilog HDL Declaration information at %2!s!: \"%1!s!\" is declared here" 0 0}
{ "Error" "EVRFX_VERI_MODULE_IGNORED" "alu alu.v(85) " "Error (10112): Ignored module \"alu\" at alu.v(85) due to previous errors" {  } { { "alu.v" "" { Text "F:/xf/alu-div/alu.v" 85 0 0 } }  } 0 10112 "Ignored module \"%1!s!\" at %2!s! due to previous errors" 0 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "alu.v 0 0 " "Info: Found 0 design units, including 0 entities, in source file alu.v" {  } {  } 0 0 "Found %2!d! design units, including %3!d! entities, in source file %1!s!" 0 0}
{ "Error" "EQEXE_ERROR_COUNT" "Analysis & Synthesis 3 s 0 s Quartus II " "Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings" { { "Error" "EQEXE_END_BANNER_TIME" "Sun Jul 08 23:19:09 2007 " "Error: Processing ended: Sun Jul 08 23:19:09 2007" {  } {  } 0 0 "Processing ended: %1!s!" 0 0} { "Error" "EQEXE_ELAPSED_TIME" "00:00:01 " "Error: Elapsed time: 00:00:01" {  } {  } 0 0 "Elapsed time: %1!s!" 0 0}  } {  } 0 0 "%6!s! %1!s! was unsuccessful. %2!d! error%3!s!, %4!d! warning%5!s!" 0 0}
{ "Info" "IRDB_WROTE_SUPPRESSED_MSGS" "F:/xf/alu-div/alu.map.smsg " "Info: Generated suppressed messages file F:/xf/alu-div/alu.map.smsg" {  } {  } 0 0 "Generated suppressed messages file %1!s!" 0 0}